fifo_dc1k16.vhd

DSP并行读取串行接口A/D芯片的VHDL接口程序

        port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);

    FF_49: FD1S3DX
        port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);

    FF_48: FD1S3DX
        port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);

    FF_47: FD1S3DX
        port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, 
            Q=>w_gcount_r10);

    FF_46: FD1S3DX
        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);

    FF_45: FD1S3DX
        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);

    FF_44: FD1S3DX
        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);

    FF_43: FD1S3DX
        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);

    FF_42: FD1S3DX
        port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);

    FF_41: FD1S3DX
        port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);

    FF_40: FD1S3DX
        port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);

    FF_39: FD1S3DX
        port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);

    FF_38: FD1S3DX
        port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);

    FF_37: FD1S3DX
        port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);

    FF_36: FD1S3DX
        port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);

    FF_35: FD1S3DX
        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
            Q=>w_gcount_r20);

    FF_34: FD1S3DX
        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
            Q=>w_gcount_r21);

    FF_33: FD1S3DX
        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
            Q=>w_gcount_r22);

    FF_32: FD1S3DX
        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
            Q=>w_gcount_r23);

    FF_31: FD1S3DX
        port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, 
            Q=>w_gcount_r24);

    FF_30: FD1S3DX
        port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, 
            Q=>w_gcount_r25);

    FF_29: FD1S3DX
        port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, 
            Q=>w_gcount_r26);

    FF_28: FD1S3DX
        port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, 
            Q=>w_gcount_r27);

    FF_27: FD1S3DX
        port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, 
            Q=>w_gcount_r28);

    FF_26: FD1S3DX
        port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, 
            Q=>w_gcount_r29);

    FF_25: FD1S3DX
        port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, 
            Q=>w_gcount_r210);

    FF_24: FD1S3DX
        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);

    FF_23: FD1S3DX
        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);

    FF_22: FD1S3DX
        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);

    FF_21: FD1S3DX
        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);

    FF_20: FD1S3DX
        port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);

    FF_19: FD1S3DX
        port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);

    FF_18: FD1S3DX
        port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);

    FF_17: FD1S3DX
        port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);

    FF_16: FD1S3DX
        port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);

    FF_15: FD1S3DX
        port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);

    FF_14: FD1S3DX
        port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, 
            Q=>r_gcount_w210);

    FF_13: FD1S3BX
        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);

    FF_12: FD1S3DX
        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);

    FF_11: FD1P3BX
        port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
            Q=>af_setcount_0);

    FF_10: FD1P3DX
        port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>af_setcount_1);

    FF_9: FD1P3DX
        port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>af_setcount_2);

    FF_8: FD1P3DX
        port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>af_setcount_3);

    FF_7: FD1P3DX
        port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>af_setcount_4);

    FF_6: FD1P3DX
        port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>af_setcount_5);

    FF_5: FD1P3DX
        port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>af_setcount_6);

    FF_4: FD1P3DX
        port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>af_setcount_7);

    FF_3: FD1P3DX
        port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>af_setcount_8);

    FF_2: FD1P3BX
        port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, PD=>Reset, 
            Q=>af_setcount_9);

    FF_1: FD1P3DX
        port map (D=>iaf_setcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>af_setcount_10);

    FF_0: FD1S3DX
        port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull);

    w_gctr_0: CU2
        port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0, 
            NC1=>iwcount_1, NC0=>iwcount_0);

    w_gctr_1: CU2
        port map (CI=>co0, PC1=>wcount_3, PC0=>wcount_2, CO=>co1, 
            NC1=>iwcount_3, NC0=>iwcount_2);

    w_gctr_2: CU2
        port map (CI=>co1, PC1=>wcount_5, PC0=>wcount_4, CO=>co2, 
            NC1=>iwcount_5, NC0=>iwcount_4);

    w_gctr_3: CU2
        port map (CI=>co2, PC1=>wcount_7, PC0=>wcount_6, CO=>co3, 
            NC1=>iwcount_7, NC0=>iwcount_6);

    w_gctr_4: CU2
        port map (CI=>co3, PC1=>wcount_9, PC0=>wcount_8, CO=>co4, 
            NC1=>iwcount_9, NC0=>iwcount_8);

    w_gctr_5: CU2
        port map (CI=>co4, PC1=>scuba_vlo, PC0=>wcount_10, CO=>co5, 
            NC1=>open, NC0=>iwcount_10);

    r_gctr_0: CU2
        port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_1, 
            NC1=>ircount_1, NC0=>ircount_0);

    r_gctr_1: CU2
        port map (CI=>co0_1, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_1, 
            NC1=>ircount_3, NC0=>ircount_2);

    r_gctr_2: CU2
        port map (CI=>co1_1, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_1, 
            NC1=>ircount_5, NC0=>ircount_4);

    r_gctr_3: CU2
        port map (CI=>co2_1, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_1, 
            NC1=>ircount_7, NC0=>ircount_6);

    r_gctr_4: CU2
        port map (CI=>co3_1, PC1=>rcount_9, PC0=>rcount_8, CO=>co4_1, 
            NC1=>ircount_9, NC0=>ircount_8);

    r_gctr_5: CU2
        port map (CI=>co4_1, PC1=>scuba_vlo, PC0=>rcount_10, CO=>co5_1, 
            NC1=>open, NC0=>ircount_10);

    empty_cmp_0: AGEB2
        port map (A1=>rcount_1, A0=>rcount_0, B1=>wcount_r1, 
            B0=>wcount_r0, CI=>rden_i, GE=>co0_2);

    empty_cmp_1: AGEB2
        port map (A1=>rcount_3, A0=>rcount_2, B1=>wcount_r3, 
            B0=>wcount_r2, CI=>co0_2, GE=>co1_2);

    empty_cmp_2: AGEB2
        port map (A1=>rcount_5, A0=>rcount_4, B1=>wcount_r5, 
            B0=>wcount_r4, CI=>co1_2, GE=>co2_2);

    empty_cmp_3: AGEB2
        port map (A1=>rcount_7, A0=>rcount_6, B1=>w_g2b_xor_cluster_0, 
            B0=>wcount_r6, CI=>co2_2, GE=>co3_2);

    empty_cmp_4: AGEB2
        port map (A1=>rcount_9, A0=>rcount_8, B1=>wcount_r9, 
            B0=>wcount_r8, CI=>co3_2, GE=>co4_2);

    empty_cmp_5: AGEB2
        port map (A1=>scuba_vlo, A0=>empty_cmp_set, B1=>scuba_vlo, 
            B0=>empty_cmp_clr, CI=>co4_2, GE=>empty_d_c);

    a0: FADD2
        port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo, 
            B0=>scuba_vlo, CI=>empty_d_c, COUT1=>open, COUT0=>open, 
            S1=>open, S0=>empty_d);

    full_cmp_0: AGEB2
        port map (A1=>wcount_1, A0=>wcount_0, B1=>rcount_w1, 
            B0=>rcount_w0, CI=>wren_i, GE=>co0_3);

    full_cmp_1: AGEB2
        port map (A1=>wcount_3, A0=>wcount_2, B1=>rcount_w3, 
            B0=>rcount_w2, CI=>co0_3, GE=>co1_3);

    full_cmp_2: AGEB2
        port map (A1=>wcount_5, A0=>wcount_4, B1=>rcount_w5, 
            B0=>rcount_w4, CI=>co1_3, GE=>co2_3);

    full_cmp_3: AGEB2
        port map (A1=>wcount_7, A0=>wcount_6, B1=>r_g2b_xor_cluster_0, 
            B0=>rcount_w6, CI=>co2_3, GE=>co3_3);

    full_cmp_4: AGEB2
        port map (A1=>wcount_9, A0=>wcount_8, B1=>rcount_w9, 
            B0=>rcount_w8, CI=>co3_3, GE=>co4_3);

    full_cmp_5: AGEB2
        port map (A1=>scuba_vlo, A0=>full_cmp_set, B1=>scuba_vlo, 
            B0=>full_cmp_clr, CI=>co4_3, GE=>full_d_c);

    a1: FADD2
        port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo, 
            B0=>scuba_vlo, CI=>full_d_c, COUT1=>open, COUT0=>open, 
            S1=>open, S0=>full_d);

    scuba_vhi_inst: VHI
        port map (Z=>scuba_vhi);

    af_set_ctr_0: CU2
        port map (CI=>scuba_vhi, PC1=>af_setcount_1, PC0=>af_setcount_0, 
            CO=>co0_4, NC1=>iaf_setcount_1, NC0=>iaf_setcount_0);

    af_set_ctr_1: CU2
        port map (CI=>co0_4, PC1=>af_setcount_3, PC0=>af_setcount_2, 
            CO=>co1_4, NC1=>iaf_setcount_3, NC0=>iaf_setcount_2);

    af_set_ctr_2: CU2
        port map (CI=>co1_4, PC1=>af_setcount_5, PC0=>af_setcount_4, 
            CO=>co2_4, NC1=>iaf_setcount_5, NC0=>iaf_setcount_4);

    af_set_ctr_3: CU2
        port map (CI=>co2_4, PC1=>af_setcount_7, PC0=>af_setcount_6, 
            CO=>co3_4, NC1=>iaf_setcount_7, NC0=>iaf_setcount_6);

    af_set_ctr_4: CU2
        port map (CI=>co3_4, PC1=>af_setcount_9, PC0=>af_setcount_8, 
            CO=>co4_4, NC1=>iaf_setcount_9, NC0=>iaf_setcount_8);

    af_set_ctr_5: CU2
        port map (CI=>co4_4, PC1=>scuba_vlo, PC0=>af_setcount_10, 
            CO=>co5_2, NC1=>open, NC0=>iaf_setcount_10);

    af_set_cmp_0: AGEB2
        port map (A1=>af_setcount_1, A0=>af_setcount_0, B1=>rcount_w1, 
            B0=>rcount_w0, CI=>wren_i, GE=>co0_5);

    af_set_cmp_1: AGEB2
        port map (A1=>af_setcount_3, A0=>af_setcount_2, B1=>rcount_w3, 
            B0=>rcount_w2, CI=>co0_5, GE=>co1_5);

    af_set_cmp_2: AGEB2
        port map (A1=>af_setcount_5, A0=>af_setcount_4, B1=>rcount_w5, 
            B0=>rcount_w4, CI=>co1_5, GE=>co2_5);

    af_set_cmp_3: AGEB2
        port map (A1=>af_setcount_7, A0=>af_setcount_6, 
            B1=>r_g2b_xor_cluster_0, B0=>rcount_w6, CI=>co2_5, GE=>co3_5);

    af_set_cmp_4: AGEB2
        port map (A1=>af_setcount_9, A0=>af_setcount_8, B1=>rcount_w9, 
            B0=>rcount_w8, CI=>co3_5, GE=>co4_5);

    af_set_cmp_5: AGEB2
        port map (A1=>scuba_vlo, A0=>af_set_cmp_set, B1=>scuba_vlo, 
            B0=>af_set_cmp_clr, CI=>co4_5, GE=>af_set_c);

    scuba_vlo_inst: VLO
        port map (Z=>scuba_vlo);

    a2: FADD2
        port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo, 
            B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open, 
            S1=>open, S0=>af_set);

    Empty <= empty_i;
    Full <= full_i;
end Structure;

-- synopsys translate_off
library xp;
configuration Structure_CON of FIFO_DC1K16 is
    for Structure
        for all:PDP8KA use entity xp.PDP8KA(V); end for;
        for all:AGEB2 use entity xp.AGEB2(V); end for;
        for all:AND2 use entity xp.AND2(V); end for;
        for all:CU2 use entity xp.CU2(V); end for;
        for all:FADD2 use entity xp.FADD2(V); end for;
        for all:FD1P3BX use entity xp.FD1P3BX(V); end for;
        for all:FD1P3DX use entity xp.FD1P3DX(V); end for;
        for all:FD1S3BX use entity xp.FD1S3BX(V); end for;
        for all:FD1S3DX use entity xp.FD1S3DX(V); end for;
        for all:INV use entity xp.INV(V); end for;
        for all:OR2 use entity xp.OR2(V); end for;
        for all:ROM16X1 use entity xp.ROM16X1(V); end for;
        for all:VHI use entity xp.VHI(V); end for;
        for all:VLO use entity xp.VLO(V); end for;
        for all:XOR2 use entity xp.XOR2(V); end for;
    end for;
end Structure_CON;

-- synopsys translate_on