fifo_dc1k16.vhd

DSP并行读取串行接口A/D芯片的VHDL接口程序

        -- synopsys translate_on
        port map (AD3=>af_setcount_10, AD2=>wcount_10, 
            AD1=>r_gcount_w210, AD0=>wptr_10, DO0=>af_set_cmp_set);

    LUT4_0: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x8001")
        -- synopsys translate_on
        port map (AD3=>af_setcount_10, AD2=>wcount_10, 
            AD1=>r_gcount_w210, AD0=>wptr_10, DO0=>af_set_cmp_clr);

    pdp_ram_0_0_1: PDP8KA
        -- synopsys translate_off
        generic map (CSDECODE_R=> "000", CSDECODE_W=> "000", GSR=> "ENABLED", 
        RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=>  9, 
        DATA_WIDTH_W=>  9)
        -- synopsys translate_on
        port map (CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vlo, 
            CSW1=>scuba_vlo, CSW2=>scuba_vlo, WE=>scuba_vhi, CER=>rden_i, 
            CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, 
            CSR2=>scuba_vlo, RST=>Reset, DI0=>Data(0), DI1=>Data(1), 
            DI2=>Data(2), DI3=>Data(3), DI4=>Data(4), DI5=>Data(5), 
            DI6=>Data(6), DI7=>Data(7), DI8=>Data(8), DI9=>scuba_vlo, 
            DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo, 
            DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo, 
            DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>Data(0), 
            DI19=>Data(1), DI20=>Data(2), DI21=>Data(3), DI22=>Data(4), 
            DI23=>Data(5), DI24=>Data(6), DI25=>Data(7), DI26=>Data(8), 
            DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo, 
            DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo, 
            DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, 
            ADW0=>scuba_vlo, ADW1=>scuba_vlo, ADW2=>scuba_vlo, 
            ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2, ADW6=>wptr_3, 
            ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6, ADW10=>wptr_7, 
            ADW11=>wptr_8, ADW12=>wptr_9, ADR0=>scuba_vlo, 
            ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1, 
            ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5, 
            ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9, 
            DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), DO4=>Q(4), 
            DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8), DO9=>open, 
            DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open, 
            DO15=>open, DO16=>open, DO17=>open, DO18=>open, DO19=>open, 
            DO20=>open, DO21=>open, DO22=>open, DO23=>open, DO24=>open, 
            DO25=>open, DO26=>open, DO27=>open, DO28=>open, DO29=>open, 
            DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open, 
            DO35=>open);

    pdp_ram_0_1_0: PDP8KA
        -- synopsys translate_off
        generic map (CSDECODE_R=> "000", CSDECODE_W=> "000", GSR=> "ENABLED", 
        RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=>  9, 
        DATA_WIDTH_W=>  9)
        -- synopsys translate_on
        port map (CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vlo, 
            CSW1=>scuba_vlo, CSW2=>scuba_vlo, WE=>scuba_vhi, CER=>rden_i, 
            CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, 
            CSR2=>scuba_vlo, RST=>Reset, DI0=>Data(9), DI1=>Data(10), 
            DI2=>Data(11), DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), 
            DI6=>Data(15), DI7=>scuba_vlo, DI8=>scuba_vlo, 
            DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>scuba_vlo, 
            DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo, 
            DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo, 
            DI18=>Data(9), DI19=>Data(10), DI20=>Data(11), 
            DI21=>Data(12), DI22=>Data(13), DI23=>Data(14), 
            DI24=>Data(15), DI25=>scuba_vlo, DI26=>scuba_vlo, 
            DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo, 
            DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo, 
            DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, 
            ADW0=>scuba_vlo, ADW1=>scuba_vlo, ADW2=>scuba_vlo, 
            ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2, ADW6=>wptr_3, 
            ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6, ADW10=>wptr_7, 
            ADW11=>wptr_8, ADW12=>wptr_9, ADR0=>scuba_vlo, 
            ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1, 
            ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5, 
            ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9, 
            DO0=>Q(9), DO1=>Q(10), DO2=>Q(11), DO3=>Q(12), DO4=>Q(13), 
            DO5=>Q(14), DO6=>Q(15), DO7=>open, DO8=>open, DO9=>open, 
            DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open, 
            DO15=>open, DO16=>open, DO17=>open, DO18=>open, DO19=>open, 
            DO20=>open, DO21=>open, DO22=>open, DO23=>open, DO24=>open, 
            DO25=>open, DO26=>open, DO27=>open, DO28=>open, DO29=>open, 
            DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open, 
            DO35=>open);

    FF_123: FD1P3BX
        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
            Q=>wcount_0);

    FF_122: FD1P3DX
        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wcount_1);

    FF_121: FD1P3DX
        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wcount_2);

    FF_120: FD1P3DX
        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wcount_3);

    FF_119: FD1P3DX
        port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wcount_4);

    FF_118: FD1P3DX
        port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wcount_5);

    FF_117: FD1P3DX
        port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wcount_6);

    FF_116: FD1P3DX
        port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wcount_7);

    FF_115: FD1P3DX
        port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wcount_8);

    FF_114: FD1P3DX
        port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wcount_9);

    FF_113: FD1P3DX
        port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wcount_10);

    FF_112: FD1P3DX
        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>w_gcount_0);

    FF_111: FD1P3DX
        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>w_gcount_1);

    FF_110: FD1P3DX
        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>w_gcount_2);

    FF_109: FD1P3DX
        port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>w_gcount_3);

    FF_108: FD1P3DX
        port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>w_gcount_4);

    FF_107: FD1P3DX
        port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>w_gcount_5);

    FF_106: FD1P3DX
        port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>w_gcount_6);

    FF_105: FD1P3DX
        port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>w_gcount_7);

    FF_104: FD1P3DX
        port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>w_gcount_8);

    FF_103: FD1P3DX
        port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>w_gcount_9);

    FF_102: FD1P3DX
        port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>w_gcount_10);

    FF_101: FD1P3DX
        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wptr_0);

    FF_100: FD1P3DX
        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wptr_1);

    FF_99: FD1P3DX
        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wptr_2);

    FF_98: FD1P3DX
        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wptr_3);

    FF_97: FD1P3DX
        port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wptr_4);

    FF_96: FD1P3DX
        port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wptr_5);

    FF_95: FD1P3DX
        port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wptr_6);

    FF_94: FD1P3DX
        port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wptr_7);

    FF_93: FD1P3DX
        port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wptr_8);

    FF_92: FD1P3DX
        port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wptr_9);

    FF_91: FD1P3DX
        port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, 
            Q=>wptr_10);

    FF_90: FD1P3BX
        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
            Q=>rcount_0);

    FF_89: FD1P3DX
        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rcount_1);

    FF_88: FD1P3DX
        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rcount_2);

    FF_87: FD1P3DX
        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rcount_3);

    FF_86: FD1P3DX
        port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rcount_4);

    FF_85: FD1P3DX
        port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rcount_5);

    FF_84: FD1P3DX
        port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rcount_6);

    FF_83: FD1P3DX
        port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rcount_7);

    FF_82: FD1P3DX
        port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rcount_8);

    FF_81: FD1P3DX
        port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rcount_9);

    FF_80: FD1P3DX
        port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rcount_10);

    FF_79: FD1P3DX
        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>r_gcount_0);

    FF_78: FD1P3DX
        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>r_gcount_1);

    FF_77: FD1P3DX
        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>r_gcount_2);

    FF_76: FD1P3DX
        port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>r_gcount_3);

    FF_75: FD1P3DX
        port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>r_gcount_4);

    FF_74: FD1P3DX
        port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>r_gcount_5);

    FF_73: FD1P3DX
        port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>r_gcount_6);

    FF_72: FD1P3DX
        port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>r_gcount_7);

    FF_71: FD1P3DX
        port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>r_gcount_8);

    FF_70: FD1P3DX
        port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>r_gcount_9);

    FF_69: FD1P3DX
        port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>r_gcount_10);

    FF_68: FD1P3DX
        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rptr_0);

    FF_67: FD1P3DX
        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rptr_1);

    FF_66: FD1P3DX
        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rptr_2);

    FF_65: FD1P3DX
        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rptr_3);

    FF_64: FD1P3DX
        port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rptr_4);

    FF_63: FD1P3DX
        port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rptr_5);

    FF_62: FD1P3DX
        port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rptr_6);

    FF_61: FD1P3DX
        port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rptr_7);

    FF_60: FD1P3DX
        port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rptr_8);

    FF_59: FD1P3DX
        port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rptr_9);

    FF_58: FD1P3DX
        port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, 
            Q=>rptr_10);

    FF_57: FD1S3DX
        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);

    FF_56: FD1S3DX
        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);

    FF_55: FD1S3DX
        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);

    FF_54: FD1S3DX
        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);

    FF_53: FD1S3DX
        port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);

    FF_52: FD1S3DX
        port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);

    FF_51: FD1S3DX
        port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);

    FF_50: FD1S3DX