fifo_dc1k16.vhd

DSP并行读取串行接口A/D芯片的VHDL接口程序

    component FD1S3BX
        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
            Q: out  std_logic);
    end component;
    component FD1S3DX
        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
            Q: out  std_logic);
    end component;
    component INV
        port (A: in  std_logic; Z: out  std_logic);
    end component;
    component OR2
        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
    end component;
    component ROM16X1
    -- synopsys translate_off
        generic (initval : in String);
    -- synopsys translate_on
        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
            AD0: in  std_logic; DO0: out  std_logic);
    end component;
    component VHI
        port (Z: out  std_logic);
    end component;
    component VLO
        port (Z: out  std_logic);
    end component;
    component XOR2
        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
    end component;
    attribute initval : string; 
    attribute MEM_LPC_FILE : string; 
    attribute MEM_INIT_FILE : string; 
    attribute CSDECODE_R : string; 
    attribute CSDECODE_W : string; 
    attribute GSR : string; 
    attribute RESETMODE : string; 
    attribute REGMODE : string; 
    attribute DATA_WIDTH_R : string; 
    attribute DATA_WIDTH_W : string; 
    attribute initval of LUT4_29 : label is "0x6996";
    attribute initval of LUT4_28 : label is "0x6996";
    attribute initval of LUT4_27 : label is "0x6996";
    attribute initval of LUT4_26 : label is "0x6996";
    attribute initval of LUT4_25 : label is "0x6996";
    attribute initval of LUT4_24 : label is "0x6996";
    attribute initval of LUT4_23 : label is "0x6996";
    attribute initval of LUT4_22 : label is "0x6996";
    attribute initval of LUT4_21 : label is "0x6996";
    attribute initval of LUT4_20 : label is "0x6996";
    attribute initval of LUT4_19 : label is "0x6996";
    attribute initval of LUT4_18 : label is "0x6996";
    attribute initval of LUT4_17 : label is "0x6996";
    attribute initval of LUT4_16 : label is "0x6996";
    attribute initval of LUT4_15 : label is "0x6996";
    attribute initval of LUT4_14 : label is "0x6996";
    attribute initval of LUT4_13 : label is "0x6996";
    attribute initval of LUT4_12 : label is "0x6996";
    attribute initval of LUT4_11 : label is "0x6996";
    attribute initval of LUT4_10 : label is "0x6996";
    attribute initval of LUT4_9 : label is "0x6996";
    attribute initval of LUT4_8 : label is "0x6996";
    attribute initval of LUT4_7 : label is "0x6996";
    attribute initval of LUT4_6 : label is "0x6996";
    attribute initval of LUT4_5 : label is "0x0410";
    attribute initval of LUT4_4 : label is "0x1004";
    attribute initval of LUT4_3 : label is "0x0140";
    attribute initval of LUT4_2 : label is "0x4001";
    attribute initval of LUT4_1 : label is "0x4c32";
    attribute initval of LUT4_0 : label is "0x8001";
    attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "FIFO_DC1K16.lpc";
    attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
    attribute CSDECODE_R of pdp_ram_0_0_1 : label is "000";
    attribute CSDECODE_W of pdp_ram_0_0_1 : label is "000";
    attribute GSR of pdp_ram_0_0_1 : label is "ENABLED";
    attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC";
    attribute REGMODE of pdp_ram_0_0_1 : label is "NOREG";
    attribute DATA_WIDTH_R of pdp_ram_0_0_1 : label is "9";
    attribute DATA_WIDTH_W of pdp_ram_0_0_1 : label is "9";
    attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "FIFO_DC1K16.lpc";
    attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
    attribute CSDECODE_R of pdp_ram_0_1_0 : label is "000";
    attribute CSDECODE_W of pdp_ram_0_1_0 : label is "000";
    attribute GSR of pdp_ram_0_1_0 : label is "ENABLED";
    attribute RESETMODE of pdp_ram_0_1_0 : label is "ASYNC";
    attribute REGMODE of pdp_ram_0_1_0 : label is "NOREG";
    attribute DATA_WIDTH_R of pdp_ram_0_1_0 : label is "9";
    attribute DATA_WIDTH_W of pdp_ram_0_1_0 : label is "9";
    attribute syn_keep : boolean;

begin
    -- component instantiation statements
    AND2_t22: AND2
        port map (A=>WrEn, B=>invout_1, Z=>wren_i);

    INV_1: INV
        port map (A=>full_i, Z=>invout_1);

    AND2_t21: AND2
        port map (A=>RdEn, B=>invout_0, Z=>rden_i);

    INV_0: INV
        port map (A=>empty_i, Z=>invout_0);

    OR2_t20: OR2
        port map (A=>Reset, B=>RPReset, Z=>rRst);

    XOR2_t19: XOR2
        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);

    XOR2_t18: XOR2
        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);

    XOR2_t17: XOR2
        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);

    XOR2_t16: XOR2
        port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);

    XOR2_t15: XOR2
        port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);

    XOR2_t14: XOR2
        port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);

    XOR2_t13: XOR2
        port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);

    XOR2_t12: XOR2
        port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);

    XOR2_t11: XOR2
        port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);

    XOR2_t10: XOR2
        port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);

    XOR2_t9: XOR2
        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);

    XOR2_t8: XOR2
        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);

    XOR2_t7: XOR2
        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);

    XOR2_t6: XOR2
        port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);

    XOR2_t5: XOR2
        port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);

    XOR2_t4: XOR2
        port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);

    XOR2_t3: XOR2
        port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);

    XOR2_t2: XOR2
        port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);

    XOR2_t1: XOR2
        port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);

    XOR2_t0: XOR2
        port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);

    LUT4_29: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, 
            AD1=>w_gcount_r29, AD0=>w_gcount_r210, 
            DO0=>w_g2b_xor_cluster_0);

    LUT4_28: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, 
            AD1=>w_gcount_r25, AD0=>w_gcount_r26, 
            DO0=>w_g2b_xor_cluster_1);

    LUT4_27: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, AD1=>scuba_vlo, 
            AD0=>scuba_vlo, DO0=>wcount_r9);

    LUT4_26: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, 
            AD1=>w_gcount_r210, AD0=>scuba_vlo, DO0=>wcount_r8);

    LUT4_25: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, 
            AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);

    LUT4_24: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, 
            AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);

    LUT4_23: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, 
            AD1=>w_gcount_r26, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r4);

    LUT4_22: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r3);

    LUT4_21: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
            AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r2);

    LUT4_20: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
            AD1=>w_gcount_r21, AD0=>w_gcount_r22, DO0=>wcount_r1);

    LUT4_19: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, 
            AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_2);

    LUT4_18: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, 
            AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);

    LUT4_17: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, 
            AD1=>r_gcount_w29, AD0=>r_gcount_w210, 
            DO0=>r_g2b_xor_cluster_0);

    LUT4_16: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, 
            AD1=>r_gcount_w25, AD0=>r_gcount_w26, 
            DO0=>r_g2b_xor_cluster_1);

    LUT4_15: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>scuba_vlo, 
            AD0=>scuba_vlo, DO0=>rcount_w9);

    LUT4_14: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, 
            AD1=>r_gcount_w210, AD0=>scuba_vlo, DO0=>rcount_w8);

    LUT4_13: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, 
            AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6);

    LUT4_12: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, 
            AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);

    LUT4_11: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, 
            AD1=>r_gcount_w26, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w4);

    LUT4_10: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
            AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w3);

    LUT4_9: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
            AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w2);

    LUT4_8: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
            AD1=>r_gcount_w21, AD0=>r_gcount_w22, DO0=>rcount_w1);

    LUT4_7: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, 
            AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2);

    LUT4_6: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x6996")
        -- synopsys translate_on
        port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, 
            AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0);

    LUT4_5: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x0410")
        -- synopsys translate_on
        port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r210, 
            AD0=>scuba_vlo, DO0=>empty_cmp_set);

    LUT4_4: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x1004")
        -- synopsys translate_on
        port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r210, 
            AD0=>scuba_vlo, DO0=>empty_cmp_clr);

    LUT4_3: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x0140")
        -- synopsys translate_on
        port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w210, 
            AD0=>scuba_vlo, DO0=>full_cmp_set);

    LUT4_2: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x4001")
        -- synopsys translate_on
        port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w210, 
            AD0=>scuba_vlo, DO0=>full_cmp_clr);

    LUT4_1: ROM16X1
        -- synopsys translate_off
        generic map (initval=> "0x4c32")