fifo_dc1k16.vhd

DSP并行读取串行接口A/D芯片的VHDL接口程序

-- VHDL netlist generated by SCUBA ispLever_v61_SP1_Build (17)
-- Module  Version: 4.1
--F:\ispTOOLS6_1\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch mg5g00 -type ebfifo -depth 1024 -width 16 -depth 1024 -no_enable -pe -1 -pf 512 -e 

-- Mon Nov 05 11:43:16 2007

library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library xp;
use xp.components.all;
-- synopsys translate_on

entity FIFO_DC1K16 is
    port (
        Data: in  std_logic_vector(15 downto 0); 
        WrClock: in  std_logic; 
        RdClock: in  std_logic; 
        WrEn: in  std_logic; 
        RdEn: in  std_logic; 
        Reset: in  std_logic; 
        RPReset: in  std_logic; 
        Q: out  std_logic_vector(15 downto 0); 
        Empty: out  std_logic; 
        Full: out  std_logic; 
        AlmostFull: out  std_logic);
end FIFO_DC1K16;

architecture Structure of FIFO_DC1K16 is

    -- internal signal declarations
    signal invout_1: std_logic;
    signal invout_0: std_logic;
    signal w_g2b_xor_cluster_2: std_logic;
    signal w_g2b_xor_cluster_1: std_logic;
    signal r_g2b_xor_cluster_2: std_logic;
    signal r_g2b_xor_cluster_1: std_logic;
    signal w_gdata_0: std_logic;
    signal w_gdata_1: std_logic;
    signal w_gdata_2: std_logic;
    signal w_gdata_3: std_logic;
    signal w_gdata_4: std_logic;
    signal w_gdata_5: std_logic;
    signal w_gdata_6: std_logic;
    signal w_gdata_7: std_logic;
    signal w_gdata_8: std_logic;
    signal w_gdata_9: std_logic;
    signal wptr_0: std_logic;
    signal wptr_1: std_logic;
    signal wptr_2: std_logic;
    signal wptr_3: std_logic;
    signal wptr_4: std_logic;
    signal wptr_5: std_logic;
    signal wptr_6: std_logic;
    signal wptr_7: std_logic;
    signal wptr_8: std_logic;
    signal wptr_9: std_logic;
    signal wptr_10: std_logic;
    signal r_gdata_0: std_logic;
    signal r_gdata_1: std_logic;
    signal r_gdata_2: std_logic;
    signal r_gdata_3: std_logic;
    signal r_gdata_4: std_logic;
    signal r_gdata_5: std_logic;
    signal r_gdata_6: std_logic;
    signal r_gdata_7: std_logic;
    signal r_gdata_8: std_logic;
    signal r_gdata_9: std_logic;
    signal rptr_0: std_logic;
    signal rptr_1: std_logic;
    signal rptr_2: std_logic;
    signal rptr_3: std_logic;
    signal rptr_4: std_logic;
    signal rptr_5: std_logic;
    signal rptr_6: std_logic;
    signal rptr_7: std_logic;
    signal rptr_8: std_logic;
    signal rptr_9: std_logic;
    signal rptr_10: std_logic;
    signal w_gcount_0: std_logic;
    signal w_gcount_1: std_logic;
    signal w_gcount_2: std_logic;
    signal w_gcount_3: std_logic;
    signal w_gcount_4: std_logic;
    signal w_gcount_5: std_logic;
    signal w_gcount_6: std_logic;
    signal w_gcount_7: std_logic;
    signal w_gcount_8: std_logic;
    signal w_gcount_9: std_logic;
    signal w_gcount_10: std_logic;
    signal r_gcount_0: std_logic;
    signal r_gcount_1: std_logic;
    signal r_gcount_2: std_logic;
    signal r_gcount_3: std_logic;
    signal r_gcount_4: std_logic;
    signal r_gcount_5: std_logic;
    signal r_gcount_6: std_logic;
    signal r_gcount_7: std_logic;
    signal r_gcount_8: std_logic;
    signal r_gcount_9: std_logic;
    signal r_gcount_10: std_logic;
    signal w_gcount_r20: std_logic;
    signal w_gcount_r0: std_logic;
    signal w_gcount_r21: std_logic;
    signal w_gcount_r1: std_logic;
    signal w_gcount_r22: std_logic;
    signal w_gcount_r2: std_logic;
    signal w_gcount_r23: std_logic;
    signal w_gcount_r3: std_logic;
    signal w_gcount_r24: std_logic;
    signal w_gcount_r4: std_logic;
    signal w_gcount_r25: std_logic;
    signal w_gcount_r5: std_logic;
    signal w_gcount_r26: std_logic;
    signal w_gcount_r6: std_logic;
    signal w_gcount_r27: std_logic;
    signal w_gcount_r7: std_logic;
    signal w_gcount_r28: std_logic;
    signal w_gcount_r8: std_logic;
    signal w_gcount_r29: std_logic;
    signal w_gcount_r9: std_logic;
    signal w_gcount_r210: std_logic;
    signal w_gcount_r10: std_logic;
    signal r_gcount_w20: std_logic;
    signal r_gcount_w0: std_logic;
    signal r_gcount_w21: std_logic;
    signal r_gcount_w1: std_logic;
    signal r_gcount_w22: std_logic;
    signal r_gcount_w2: std_logic;
    signal r_gcount_w23: std_logic;
    signal r_gcount_w3: std_logic;
    signal r_gcount_w24: std_logic;
    signal r_gcount_w4: std_logic;
    signal r_gcount_w25: std_logic;
    signal r_gcount_w5: std_logic;
    signal r_gcount_w26: std_logic;
    signal r_gcount_w6: std_logic;
    signal r_gcount_w27: std_logic;
    signal r_gcount_w7: std_logic;
    signal r_gcount_w28: std_logic;
    signal r_gcount_w8: std_logic;
    signal r_gcount_w29: std_logic;
    signal r_gcount_w9: std_logic;
    signal r_gcount_w210: std_logic;
    signal r_gcount_w10: std_logic;
    signal empty_i: std_logic;
    signal rRst: std_logic;
    signal full_i: std_logic;
    signal iwcount_0: std_logic;
    signal iwcount_1: std_logic;
    signal iwcount_2: std_logic;
    signal iwcount_3: std_logic;
    signal co0: std_logic;
    signal iwcount_4: std_logic;
    signal iwcount_5: std_logic;
    signal co1: std_logic;
    signal iwcount_6: std_logic;
    signal iwcount_7: std_logic;
    signal co2: std_logic;
    signal iwcount_8: std_logic;
    signal iwcount_9: std_logic;
    signal co3: std_logic;
    signal iwcount_10: std_logic;
    signal co5: std_logic;
    signal wcount_10: std_logic;
    signal co4: std_logic;
    signal ircount_0: std_logic;
    signal ircount_1: std_logic;
    signal ircount_2: std_logic;
    signal ircount_3: std_logic;
    signal co0_1: std_logic;
    signal ircount_4: std_logic;
    signal ircount_5: std_logic;
    signal co1_1: std_logic;
    signal ircount_6: std_logic;
    signal ircount_7: std_logic;
    signal co2_1: std_logic;
    signal ircount_8: std_logic;
    signal ircount_9: std_logic;
    signal co3_1: std_logic;
    signal ircount_10: std_logic;
    signal co5_1: std_logic;
    signal rcount_10: std_logic;
    signal co4_1: std_logic;
    signal rden_i: std_logic;
    signal wcount_r0: std_logic;
    signal wcount_r1: std_logic;
    signal rcount_0: std_logic;
    signal rcount_1: std_logic;
    signal co0_2: std_logic;
    signal wcount_r2: std_logic;
    signal wcount_r3: std_logic;
    signal rcount_2: std_logic;
    signal rcount_3: std_logic;
    signal co1_2: std_logic;
    signal wcount_r4: std_logic;
    signal wcount_r5: std_logic;
    signal rcount_4: std_logic;
    signal rcount_5: std_logic;
    signal co2_2: std_logic;
    signal wcount_r6: std_logic;
    signal w_g2b_xor_cluster_0: std_logic;
    signal rcount_6: std_logic;
    signal rcount_7: std_logic;
    signal co3_2: std_logic;
    signal wcount_r8: std_logic;
    signal wcount_r9: std_logic;
    signal rcount_8: std_logic;
    signal rcount_9: std_logic;
    signal co4_2: std_logic;
    signal empty_cmp_clr: std_logic;
    signal empty_cmp_set: std_logic;
    signal empty_d: std_logic;
    signal empty_d_c: std_logic;
    signal wcount_0: std_logic;
    signal wcount_1: std_logic;
    signal co0_3: std_logic;
    signal wcount_2: std_logic;
    signal wcount_3: std_logic;
    signal co1_3: std_logic;
    signal wcount_4: std_logic;
    signal wcount_5: std_logic;
    signal co2_3: std_logic;
    signal wcount_6: std_logic;
    signal wcount_7: std_logic;
    signal co3_3: std_logic;
    signal wcount_8: std_logic;
    signal wcount_9: std_logic;
    signal co4_3: std_logic;
    signal full_cmp_clr: std_logic;
    signal full_cmp_set: std_logic;
    signal full_d: std_logic;
    signal full_d_c: std_logic;
    signal iaf_setcount_0: std_logic;
    signal iaf_setcount_1: std_logic;
    signal scuba_vhi: std_logic;
    signal iaf_setcount_2: std_logic;
    signal iaf_setcount_3: std_logic;
    signal co0_4: std_logic;
    signal iaf_setcount_4: std_logic;
    signal iaf_setcount_5: std_logic;
    signal co1_4: std_logic;
    signal iaf_setcount_6: std_logic;
    signal iaf_setcount_7: std_logic;
    signal co2_4: std_logic;
    signal iaf_setcount_8: std_logic;
    signal iaf_setcount_9: std_logic;
    signal co3_4: std_logic;
    signal iaf_setcount_10: std_logic;
    signal co5_2: std_logic;
    signal af_setcount_10: std_logic;
    signal co4_4: std_logic;
    signal wren_i: std_logic;
    signal rcount_w0: std_logic;
    signal rcount_w1: std_logic;
    signal af_setcount_0: std_logic;
    signal af_setcount_1: std_logic;
    signal co0_5: std_logic;
    signal rcount_w2: std_logic;
    signal rcount_w3: std_logic;
    signal af_setcount_2: std_logic;
    signal af_setcount_3: std_logic;
    signal co1_5: std_logic;
    signal rcount_w4: std_logic;
    signal rcount_w5: std_logic;
    signal af_setcount_4: std_logic;
    signal af_setcount_5: std_logic;
    signal co2_5: std_logic;
    signal rcount_w6: std_logic;
    signal r_g2b_xor_cluster_0: std_logic;
    signal af_setcount_6: std_logic;
    signal af_setcount_7: std_logic;
    signal co3_5: std_logic;
    signal rcount_w8: std_logic;
    signal rcount_w9: std_logic;
    signal af_setcount_8: std_logic;
    signal af_setcount_9: std_logic;
    signal co4_5: std_logic;
    signal af_set_cmp_clr: std_logic;
    signal af_set_cmp_set: std_logic;
    signal af_set: std_logic;
    signal af_set_c: std_logic;
    signal scuba_vlo: std_logic;

    -- local component declarations
    component PDP8KA
    -- synopsys translate_off
        generic (CSDECODE_R : in String; CSDECODE_W : in String; 
                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer; 
                RESETMODE : in String; GSR : in String; 
                REGMODE : in String);
    -- synopsys translate_on
        port (CEW: in  std_logic; CLKW: in  std_logic; 
            CSW0: in  std_logic; CSW1: in  std_logic; 
            CSW2: in  std_logic; WE: in  std_logic; CER: in  std_logic; 
            CLKR: in  std_logic; CSR0: in  std_logic; 
            CSR1: in  std_logic; CSR2: in  std_logic; RST: in  std_logic; 
            DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
            DI12: in  std_logic; DI13: in  std_logic; 
            DI14: in  std_logic; DI15: in  std_logic; 
            DI16: in  std_logic; DI17: in  std_logic; 
            DI18: in  std_logic; DI19: in  std_logic; 
            DI20: in  std_logic; DI21: in  std_logic; 
            DI22: in  std_logic; DI23: in  std_logic; 
            DI24: in  std_logic; DI25: in  std_logic; 
            DI26: in  std_logic; DI27: in  std_logic; 
            DI28: in  std_logic; DI29: in  std_logic; 
            DI30: in  std_logic; DI31: in  std_logic; 
            DI32: in  std_logic; DI33: in  std_logic; 
            DI34: in  std_logic; DI35: in  std_logic; 
            ADW0: in  std_logic; ADW1: in  std_logic; 
            ADW2: in  std_logic; ADW3: in  std_logic; 
            ADW4: in  std_logic; ADW5: in  std_logic; 
            ADW6: in  std_logic; ADW7: in  std_logic; 
            ADW8: in  std_logic; ADW9: in  std_logic; 
            ADW10: in  std_logic; ADW11: in  std_logic; 
            ADW12: in  std_logic; ADR0: in  std_logic; 
            ADR1: in  std_logic; ADR2: in  std_logic; 
            ADR3: in  std_logic; ADR4: in  std_logic; 
            ADR5: in  std_logic; ADR6: in  std_logic; 
            ADR7: in  std_logic; ADR8: in  std_logic; 
            ADR9: in  std_logic; ADR10: in  std_logic; 
            ADR11: in  std_logic; ADR12: in  std_logic; 
            DO0: out  std_logic; DO1: out  std_logic; 
            DO2: out  std_logic; DO3: out  std_logic; 
            DO4: out  std_logic; DO5: out  std_logic; 
            DO6: out  std_logic; DO7: out  std_logic; 
            DO8: out  std_logic; DO9: out  std_logic; 
            DO10: out  std_logic; DO11: out  std_logic; 
            DO12: out  std_logic; DO13: out  std_logic; 
            DO14: out  std_logic; DO15: out  std_logic; 
            DO16: out  std_logic; DO17: out  std_logic; 
            DO18: out  std_logic; DO19: out  std_logic; 
            DO20: out  std_logic; DO21: out  std_logic; 
            DO22: out  std_logic; DO23: out  std_logic; 
            DO24: out  std_logic; DO25: out  std_logic; 
            DO26: out  std_logic; DO27: out  std_logic; 
            DO28: out  std_logic; DO29: out  std_logic; 
            DO30: out  std_logic; DO31: out  std_logic; 
            DO32: out  std_logic; DO33: out  std_logic; 
            DO34: out  std_logic; DO35: out  std_logic);
    end component;
    component AGEB2
        port (A1: in  std_logic; A0: in  std_logic; B1: in  std_logic; 
            B0: in  std_logic; CI: in  std_logic; GE: out  std_logic);
    end component;
    component AND2
        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
    end component;
    component CU2
        port (CI: in  std_logic; PC1: in  std_logic; PC0: in  std_logic; 
            CO: out  std_logic; NC1: out  std_logic; NC0: out  std_logic);
    end component;
    component FADD2
        port (A1: in  std_logic; A0: in  std_logic; B1: in  std_logic; 
            B0: in  std_logic; CI: in  std_logic; COUT1: out  std_logic; 
            COUT0: out  std_logic; S1: out  std_logic; 
            S0: out  std_logic);
    end component;
    component FD1P3BX
        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
            PD: in  std_logic; Q: out  std_logic);
    end component;
    component FD1P3DX
        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
            CD: in  std_logic; Q: out  std_logic);
    end component;