ad_ad7980.vhd

DSP并行读取串行接口A/D芯片的VHDL接口程序

-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
entity AD_AD7980 is
  port 
  (
     reset,clk,csad,read,ad_din		: in  std_logic;
     ad_cnv,clk_out								: out Std_Logic;
     data_out											: out Std_Logic_Vector(15 downto 0)	
  );
end entity; 

architecture Behaviour of AD_AD7980 is
  signal ad_value,ad_valueout     	: Std_Logic_Vector(15 downto 0); 
  signal shiften,shiften1,shiften2 	: Std_Logic;
  signal shift_cnt					: Std_Logic_Vector(4 downto 0);
  signal rclk,csadrd				: std_logic;
  signal shiften3,shiften4 	: Std_Logic;

begin
	
	csadrd <= csad or read;

	clk_out <= not (shiften1) or (not clk) or shiften2;
--  rclk <= not (shiften1) or (not clk) or shiften2;
  rclk <= shiften3 and  clk and (not shiften4);
  
  process(reset,csadrd,shift_cnt)
  begin
  	if reset = '0' or shift_cnt="10100" then
  		shiften <= '0';
 	  elsif csadrd='0' then
  		shiften <='1';
  	end if;
  end process;
 
	process(clk,shiften,shift_cnt)
	begin
  	if shiften = '0' then
  		shift_cnt <= "00000";
	  	ad_cnv <= '1';
	  	shiften1 <= '0';
	  	shiften3 <= '0';
  	elsif	clk'event and clk='1' then
			case shift_cnt is
			  when "00001" =>
			  	ad_cnv <= '0';
			  when "00010" =>
			  	shiften1 <= '1';
--			  when "00011" =>
			  	shiften3 <= '1';
			 	when "10001" =>			--10010
					shiften1 <= '0';
			 	when "10010" =>		--10011
					ad_cnv <= '1';	
					shiften3 <= '0';			
					ad_valueout <= ad_value;
				when others =>

			end case;
			shift_cnt <= shift_cnt + '1';
		end if;
  end process;
  
  process(clk,shiften,shift_cnt)
	begin
  	if shiften = '0' then
	  	shiften2 <= '0';
  	elsif	clk'event and clk='0' then
			if shift_cnt="10001" then		--10010
			  shiften2 <= '1';
			end if;
		end if;
  end process;
  
  process(clk,shiften,shift_cnt)
	begin
  	if shiften = '0' then
	  	shiften4 <= '0';
  	elsif	clk'event and clk='0' then
			if shift_cnt="10010" then			--10011
			  shiften4 <= '1';
			end if;
		end if;
  end process;

	process(rclk,ad_din)
	begin
  	if	rclk'event and rclk='1' then
	  	ad_value(15) <= ad_value(14);
	  	ad_value(14) <= ad_value(13);	  	
	  	ad_value(13) <= ad_value(12);
	  	ad_value(12) <= ad_value(11);
	  	ad_value(11) <= ad_value(10);	  	
	  	ad_value(10) <= ad_value(9);
	  	ad_value(9) <= ad_value(8);
	  	ad_value(8) <= ad_value(7);	  	
	  	ad_value(7) <= ad_value(6);
	  	ad_value(6) <= ad_value(5);
	  	ad_value(5) <= ad_value(4);	  	
	  	ad_value(4) <= ad_value(3);
	  	ad_value(3) <= ad_value(2);
	  	ad_value(2) <= ad_value(1);	  	
	  	ad_value(1) <= ad_value(0);
	  	ad_value(0) <= ad_din;
		end if;
  end process;

	process(csadrd,ad_valueout)
  begin
  	if csadrd='0' then
  		data_out <= ad_valueout;
 	  else
  		data_out <= (others => 'Z');
  	end if;
  end process;

end Behaviour; --=================== End of architecture ====================--