jitriscemitter.h

This is a resource based on j2me embedded,if you dont understand,you can connection with me .

                                CVMCPUMemSpec *self);



/**************************************************************
 * CPU code emitters - The following are prototypes of code
 * emitters required by the RISC emitter porting layer.
 **************************************************************/

/* ===== MemoryReference Emitter APIs ===================================== */

/* Purpose: Emits instructions to do a PC-relative load. 
   NOTE: This function must always emit the exact same number of
         instructions regardless of the offset passed to it.
*/
extern void
CVMCPUemitMemoryReferencePCRelative(CVMJITCompilationContext* con,
				    int opcode, int destRegID, int offset);

/* Purpose: Emits instructions to do a load/store operation. */
extern void
CVMCPUemitMemoryReference(CVMJITCompilationContext* con,
    int opcode, int destreg, int basereg, CVMCPUMemSpecToken memSpecToken);

/* Purpose: Emits instructions to do a load/store operation. */
extern void
CVMCPUemitMemoryReferenceImmediate(CVMJITCompilationContext* con,
    int opcode, int destreg, int basereg, CVMInt32 immOffset);

/* Purpose: Emits instructions to do a conditional load/store operation. */
extern void
CVMCPUemitMemoryReferenceConditional(CVMJITCompilationContext* con,
    int opcode, int destreg, int basereg, CVMCPUMemSpecToken memSpecToken,
    CVMCPUCondCode condCode);

/* Purpose: Emits instructions to do a conditional load/store operation. */
extern void
CVMCPUemitMemoryReferenceImmediateConditional(CVMJITCompilationContext* con,
    int opcode, int destreg, int basereg, CVMInt32 immOffset,
    CVMCPUCondCode condCode);

/* Purpose: Emits instructions to do a load/store operation on a C style
            array element:
        ldr valueRegID, arrayRegID[shiftOpcode(indexRegID, shiftAmount)]
    or
        str valueRegID, arrayRegID[shiftOpcode(indexRegID, shiftAmount)]
*/
extern void
CVMCPUemitArrayElementReference(CVMJITCompilationContext* con,
    int opcode, int valueRegID, int arrayRegID, int indexRegID,
    int shiftOpcode, int shiftAmount);

/* ===== 32 Bit ALU Emitter APIs ========================================== */

/* Purpose: Emits instructions to do the specified 32 bit unary ALU
            operation. */
extern void
CVMCPUemitUnaryALU(CVMJITCompilationContext *con, 
    int opcode, int destRegID, int srcRegID,
    CVMBool setcc);

/* Purpose: Emits instructions to do the specified conditional 32 bit unary
            ALU operation. */
extern void
CVMCPUemitUnaryALUConditional(CVMJITCompilationContext *con,
    int opcode, int destRegID, int srcRegID,
    CVMBool setcc, CVMCPUCondCode condCode);

/* Purpose: Emits instructions to do the specified 32 bit ALU operation. */
extern void
CVMCPUemitBinaryALU(CVMJITCompilationContext *con,
    int opcode, int destRegID, int srcRegID, CVMCPUALURhsToken aluRhsToken,
    CVMBool setcc);

/* Purpose: Emits instructions to do the specified 32 bit ALU operation. */
extern void
CVMCPUemitBinaryALUConstant(CVMJITCompilationContext *con,
    int opcode, int destRegID, int lhsRegID, CVMInt32 rhsConstValue,
    CVMBool setcc);

/* Purpose: Emits instructions to do the specified 32 bit ALU operation. */
extern void
CVMCPUemitBinaryALURegister(CVMJITCompilationContext *con,
    int opcode, int destRegID, int lhsRegID, int rhsRegID,
    CVMBool setcc);

/* Purpose: Emits instructions to do the specified conditional 32 bit ALU
            operation. */
extern void
CVMCPUemitBinaryALUConditional(CVMJITCompilationContext* con,
    int opcode, int destRegID, int lhsRegID, CVMCPUALURhsToken rhsToken,
    CVMBool setcc, CVMCPUCondCode condCode);

/* Purpose: Emits instructions to do the specified conditional 32 bit ALU
            operation. */
extern void
CVMCPUemitBinaryALUConstantConditional(CVMJITCompilationContext* con,
    int opcode, int destRegID, int lhsRegID, CVMInt32 rhsConstValue,
    CVMBool setcc, CVMCPUCondCode condCode);

/* Purpose: Emits instructions to do the specified conditional 32 bit ALU
            operation. */
extern void
CVMCPUemitBinaryALURegisterConditional(CVMJITCompilationContext* con,
   int opcode, int destRegID, int lhsRegID, int rhsRegID,
    CVMBool setcc, CVMCPUCondCode condCode);

/* Purpose: Emits instructions to do the specified shift on a 32 bit operand.*/
extern void
CVMCPUemitShiftByConstant(CVMJITCompilationContext *con,
    int opcode, int destRegID, int srcRegID, CVMUint32 shiftAmount);

/* Purpose: Emits instructions to do the specified shift on a 32 bit operand.
            The shift amount is specified in a register.  The platform
            implementation is responsible for making sure that the shift
            semantics is done in such a way that the effect is the same as if
            the shiftAmount is masked with 0x1f before the shift operation is
            done.  This is needed in order to be compliant with the VM spec.
*/
extern void
CVMCPUemitShiftByRegister(CVMJITCompilationContext *con,
    int opcode, int destRegID, int srcRegID, int shiftAmountRegID);

/*
 * Purpose: multiply by an immedate value if the platform supports it.
 */
#ifdef CVMCPU_HAS_IMUL_IMMEDIATE
extern void
CVMCPUemitMulConstant(CVMJITCompilationContext* con,
    int destreg, int lhsreg, CVMInt32 value);
#endif

/* For MULL instruction:
       destreg = (lhsreg * rhsreg)[31:0]

   For MULH instruction:
       destreg = (lhsreg * rhsreg)[63:32]

   extraReg will always be CVMCPU_INVALID_REG unless processor specific
   code decides to make use of it with a processor specific MUL opcode.
*/
extern void
CVMCPUemitMul(CVMJITCompilationContext* con,
    int opcode, int destreg, int lhsreg, int rhsreg, int extrareg);

/* ===== Emitters to load a constant =================================== */

/* Purpose: Loads a 32-bit constant into a register. */
extern void
CVMCPUemitLoadConstant(CVMJITCompilationContext *con,
    int regID, CVMInt32 v);

/* Purpose: Conditionally loads a 32-bit constant into a register. */
extern void
CVMCPUemitLoadConstantConditional(CVMJITCompilationContext *con,
    int regID, CVMInt32 v,
    CVMCPUCondCode condCode);

/* Purpose: Does a 32-bit mov into a register.. */

extern void
CVMCPUemitMove(CVMJITCompilationContext* con,
    int opcode, int destRegID, CVMCPUALURhsToken srcToken,
    CVMBool setcc);

extern void
CVMCPUemitMoveRegister(CVMJITCompilationContext* con,
    int opcode, int destRegID, int srcRegID,
    CVMBool setcc);

extern void
CVMCPUemitMoveConditional(CVMJITCompilationContext* con,
    int opcode, int destRegID, CVMCPUALURhsToken srcToken,
    CVMBool setcc, CVMCPUCondCode condCode);

extern void
CVMCPUemitMoveRegisterConditional(CVMJITCompilationContext* con,
    int opcode, int destRegID, int srcRegID,
    CVMBool setcc, CVMCPUCondCode condCode);

/* Purpose: 32-bit compare. */

extern void
CVMCPUemitCompare(CVMJITCompilationContext* con,
    int opcode, CVMCPUCondCode condCode,
    int lhsreg, CVMCPUALURhsToken rhsToken);

extern void
CVMCPUemitCompareConstant(CVMJITCompilationContext* con,
    int opcode, CVMCPUCondCode condCode,
    int lhsRegID, CVMInt32 rhsConstValue);

extern void
CVMCPUemitCompareRegister(CVMJITCompilationContext* con,
    int opcode, CVMCPUCondCode condCode,
    int lhsRegID, int rhsRegID);

/* Purpose: emit a nop. */

extern void
CVMCPUemitNop(CVMJITCompilationContext* con);

#ifdef CVMJIT_SIMPLE_SYNC_METHODS
#if CVM_FASTLOCK_TYPE == CVM_FASTLOCK_MICROLOCK && \
    CVM_MICROLOCK_TYPE == CVM_MICROLOCK_SWAP_SPINLOCK
/*
 * Purpose: Emits an atomic swap operation. The value to swap in is in
 *          destReg, which is also where the swapped out value will be placed.
 */
extern void
CVMCPUemitAtomicSwap(CVMJITCompilationContext* con,
		     int destReg, int addressReg);
#elif CVM_FASTLOCK_TYPE == CVM_FASTLOCK_ATOMICOPS
/*
 * Purpose: Does an atomic compare-and-swap operation of newValReg into
 *          the address addressReg+addressOffset if the current value in
 *          the address is oldValReg. oldValReg and newValReg may
 *          be clobbered.
 * Return:  The int returned is the logical PC of the instruction that
 *          branches if the atomic compare-and-swap fails. It will be
 *          patched by the caller to branch to the proper failure address.
 */
extern int
CVMCPUemitAtomicCompareAndSwap(CVMJITCompilationContext* con,
			       int addressReg, int addressOffset,
			       int oldValReg, int newValReg);
#else
#error Unsupported locking type for CVMJIT_SIMPLE_SYNC_METHODS
#endif
#endif /* CVMJIT_SIMPLE_SYNC_METHODS */

/* Purpose: Emits code to computes the following expression and stores the
            result in the specified destReg:

        dest = baseReg opcode (indexReg shiftOpcode #shiftAmount)

            where opcode is a binary ALU operation and shiftOpcode is a
            shift operator that shifts the indexReg by the shiftAmount.
*/
extern void
CVMCPUemitComputeAddressOfArrayElement(CVMJITCompilationContext *con,
                                       int opcode, int destRegID,
                                       int baseRegID, int indexRegID,
                                       int shiftOpcode, int shiftAmount);

/* ===== Floating Point Emitter APIs ====================================== */
#ifdef CVM_JIT_USE_FP_HARDWARE
extern void
CVMCPUemitBinaryFP(CVMJITCompilationContext *con, int opcode,
                   int destRegID, int lhsRegID, int rhsRegID);

extern void
CVMCPUemitUnaryFP(CVMJITCompilationContext *con, int opcode,
                   int destRegID, int srcRegID);

extern void
CVMCPUemitFCompare(CVMJITCompilationContext *con, int opcode,
                   CVMCPUCondCode condCode, int lhsRegID, int rhsRegID);

/* Purpose: Loads a 32-bit constant into a floating-point register. */
/* the value is just bits to us. If it started as a floating-point number,
 * you'd better cast it carefully.
 */
extern void
CVMCPUemitLoadConstantFP(CVMJITCompilationContext *con,
    int regID, CVMInt32 v);

extern void
CVMCPUemitLoadLongConstantFP(CVMJITCompilationContext *con,
    int regID, CVMJavaVal64 *value);

#endif

/* ===== 64 Bit Emitter APIs ============================================== */

/* Purpose: Emits instructions to do the specified 64 bit unary ALU
            operation. */
extern void
CVMCPUemitUnaryALU64(CVMJITCompilationContext *con, int opcode,
                     int destRegID, int srcRegID);

/* Purpose: Emits instructions to do the specified 64 bit ALU operation. */
extern void
CVMCPUemitBinaryALU64(CVMJITCompilationContext *con,
		      int opcode, int destRegID, int lhsRegID, int rhsRegID);

/* Purpose: Loads a 64-bit integer constant into a register. */
extern void
CVMCPUemitLoadLongConstant(CVMJITCompilationContext *con, int regID,
                           CVMJavaVal64 *value);

/* Purpose: Emits instructions to compares 2 64 bit integers for the specified
            condition. 
   Return: The returned condition code may have been transformed by the
           comparison instructions because the emitter may choose to implement
           the comparison in a different form.  For example, a less than
           comparison can be implemented as a greater than comparison when
           the 2 arguments are swapped.  The returned condition code indicates
           the actual comparison operation that was emitted.
*/
CVMCPUCondCode
CVMCPUemitCompare64(CVMJITCompilationContext *con, int opcode,
                    CVMCPUCondCode condCode, int lhsRegID, int rhsRegID);

/* Purpose: Emits instructions to convert a 32 bit int into a 64 bit int. */
extern void
CVMCPUemitInt2Long(CVMJITCompilationContext *con, int destRegID, int srcRegID);

/* Purpose: Emits instructions to convert a 64 bit int into a 32 bit int. */
extern void
CVMCPUemitLong2Int(CVMJITCompilationContext *con, int destRegID, int srcRegID);

/* ===== Flow Control Emitter APIs ======================================== */

extern void
CVMCPUemitPopFrame(CVMJITCompilationContext* con, int resultSize);

/*
 * Move the JSR return address into regno. This is a no-op on
 * cpu's where the CVMCPU_JSR_RETURN_ADDRESS_SET == LR.
 */
extern void
CVMCPUemitLoadReturnAddress(CVMJITCompilationContext* con, int regno);

/*
 * Branch to the address in the specified register.
 */
void
CVMCPUemitRegisterBranch(CVMJITCompilationContext* con, int regno);

/*
 * Do a branch for a tableswitch. We need to branch into the dispatch
 * table. The target address for index 0 is located at
 * pc + 2 * CVMCPU_INSTRUCTION_SIZE, assuming that branches are always
 * done as a single instruction.
 * The branch should only be done if the compare succeeded. Otherwise
 * we just need to fall through to the default case.
 */
void
CVMCPUemitTableSwitchBranch(CVMJITCompilationContext* con, int indexRegNo);

/*
 * Emit code to do a gc rendezvous. The second argument 'cbufRewind'
 * tells the emitter if there is a code buffer rewinding, so whichever
 * instructions are emitted next just overwrite the instructions emitted
 * by CVMCPUemitGcCheck. This is done to support patching of gc checkpoints
 * so they have zero cost until a gc is needed.
 */
#ifdef CVMJIT_PATCH_BASED_GC_CHECKS
void
CVMCPUemitGcCheck(CVMJITCompilationContext* con, CVMBool cbufRewind);
#endif

/*
 * Make a PC-relative branch or branch-and-link instruction
 */

extern void
CVMCPUemitBranch(CVMJITCompilationContext* con, 
		 int logicalPC, CVMCPUCondCode condCode);

extern void
CVMCPUemitBranchLink(CVMJITCompilationContext* con, int logicalPC );

/*
 * Make a PC-relative branch or branch-and-link instruction, and
 * add the branch instruction(s) to the target fixup list.
 */
extern void
CVMCPUemitBranchNeedFixup(CVMJITCompilationContext* con, 
		          int logicalPC, CVMCPUCondCode condCode,
                          CVMJITFixupElement** fixupList);

extern void
CVMCPUemitBranchLinkNeedFixup(CVMJITCompilationContext* con, int logicalPC,
                              CVMJITFixupElement** fixupList);