jitriscemitterdefs_cpu.h

This is a resource based on j2me embedded,if you dont understand,you can connection with me .

#define CVMARM_F2I_OPCODE ((0x1d << 23) | (0x3 << 20) | (0xd << 16) \
                         | (0xa << 8) | (0x1 << 7) | (0x1 << 6)) 
#define CVMARM_I2D_OPCODE ((0x1d << 23) | (0x3 << 20) | (0x8 << 16) \
                         | (0xb << 8) | (0x1 << 7) | (0x1 << 6)) 
#define CVMARM_D2I_OPCODE ((0x1d << 23) | (0x3 << 20) | (0xd << 16) \
                         | (0xb << 8) | (0x1 << 7) | (0x1 << 6)) 
#define CVMARM_F2D_OPCODE ((0x1d << 23) | (0x3 << 20) | (0x7 << 16) \
                         | (0xa << 8) | (0x1 << 7) | (0x1 << 6)) 
#define CVMARM_D2F_OPCODE ((0x1d << 23) | (0x3 << 20) | (0x7 << 16) \
                         | (0xb << 8) | (0x1 << 7) | (0x1 << 6)) 

/* Floating-point comparison opcodes: */
/* Used only within ARM-specific code generation */
#define CVMARM_FMSTAT_OPCODE ((0xef1fa << 8) | (0x1 << 4))
#define CVMARM_FCMPES_OPCODE ((0x1d << 23) | (0x3 << 20) | (0x4 << 16) \
                            | (0xa << 8) | (0x1 << 7) | (0x1 << 6))
#define CVMARM_DCMPED_OPCODE ((0x1d << 23) | (0x3 << 20) | (0x4 << 16) \
                            | (0xb << 8) | (0x1 << 7) | (0x1 << 6))

/* Floating-point move to general purpose register opcodes: */
/* Used only within ARM-specific code generation */
#define CVMARM_MOVFA_OPCODE ((0xe0 << 20) | (0xa << 8) | 0x10) /* FMSR */
#define CVMARM_MOVAF_OPCODE ((0xe1 << 20) | (0xa << 8) | 0x10) /* FMRS */
#define CVMARM_MOVDA_OPCODE ((0xc4 << 20) | (0xb << 8) | (0x01 << 4)) /* FMDRR */
#define CVMARM_MOVAD_OPCODE ((0xc5 << 20) | (0xb << 8) | (0x01 << 4)) /* FMRRD */


/* Floating-point status register opcodes: */
#define CVMARM_FPSID 0x00000000
#define CVMARM_FPSCR 0x00000001
#define CVMARM_FPEXC 0x00001000
#define CVMARM_MOVSA_OPCODE ((0xee << 20) | (0xa << 8) | 0x10) /* FMXR */
#define CVMARM_MOVAS_OPCODE ((0xeF << 20) | (0xa << 8) | 0x10) /* FMRX */


/* 64 bit ALU opcodes:
 * NOTE: The ALU64 opcodes are actually encoded in terms of 2 32 bit ARM
 *       opcodes and a boolean:
 *           ((lowOpcode << 16) | (highOpcode << 8) | setCCForLowOpcode)
 */
#define CVMCPU_NEG64_OPCODE 0x00000006
#define CVMCPU_ADD64_OPCODE ((0x08 << 16)|(0x0a << 8)|1) /* ADD,ADC,true */
#define CVMCPU_SUB64_OPCODE ((0x04 << 16)|(0x0c << 8)|1) /* SUB,SBC,true */
#define CVMCPU_AND64_OPCODE ((0x00 << 16)|(0x00 << 8)|0) /* AND,AND,false */
#define CVMCPU_OR64_OPCODE  ((0x18 << 16)|(0x18 << 8)|0) /* OR,OR,false */
#define CVMCPU_XOR64_OPCODE ((0x02 << 16)|(0x02 << 8)|0) /* XOR,XOR,false */

#define CVMCPU_MUL64_OPCODE 0x00000007
#define CVMCPU_DIV64_OPCODE 0x00000008
#define CVMCPU_REM64_OPCODE 0x00000009
#define CVMCPU_CMP64_OPCODE 0x0000000a

/**************************************************************
 * CPU ALURhs and associated types - The following are definition
 * of the types for the ALURhs abstraction required by the RISC
 * emitter porting layer.
 **************************************************************/

/* In the ARM implementation the CVMCPUALURhs (i.e. the struct used to
 * represent an "aluRhs" operand) can have up to two register designations and
 * a shift direction packed into a single 'addressing' mode.  CVMCPUALURhs
 * pointers can be managed as elements of the code-gen time semantic stack.
 */

typedef enum {
    CVMARM_ALURHS_CONSTANT,
    CVMARM_ALURHS_SHIFT_BY_REGISTER,
    CVMARM_ALURHS_SHIFT_BY_CONSTANT
} CVMARMALURhsType;

/*
 * We could use a union to make this more compact,
 * but at much loss of clarity.
 */
typedef struct {
    CVMARMALURhsType    type;
    int                 shiftOp;
    CVMInt32            constValue;
    CVMRMResource*      r1;
    CVMRMResource*      r2;
} CVMCPUALURhs;

typedef CVMUint32 CVMCPUALURhsToken;

/* ARM specific ALURhs encoding bits: */
#define CVMARM_MODE1_CONSTANT       (1 << 25)
#define CVMARM_MODE1_SHIFT_CONSTANT (0) 
#define CVMARM_MODE1_SHIFT_REGISTER (1 << 4)

#define CVMCPUALURhsTokenConstZero  (1 << 25) /* Mode 1 constant 0. */

/**************************************************************
 * CPU MemSpec and associated types - The following are definition
 * of the types for the MemSpec abstraction required by the RISC
 * emitter porting layer.
 **************************************************************/

typedef enum {
    CVMCPU_MEMSPEC_IMMEDIATE_OFFSET,
    CVMCPU_MEMSPEC_REG_OFFSET,
    CVMCPU_MEMSPEC_POSTINCREMENT_IMMEDIATE_OFFSET,
    CVMCPU_MEMSPEC_PREDECREMENT_IMMEDIATE_OFFSET
} CVMCPUMemSpecType;

/* Class: CVMCPUMemSpec
   Purpose: Encapsulates the parameters for encoding a memory access
            specification for the use of a memory reference instruction.
*/
typedef struct CVMCPUMemSpec CVMCPUMemSpec;
struct CVMCPUMemSpec {
    CVMCPUMemSpecType type;

    /* The following are the parameters needed to encode the fields in a
       memory reference instruction.  The method of encoding is determined by
       the addressMode above.  The field which are specific to each address
       mode could be set up as a union for compactness but is left as below
       for clarity. */

    /* Address mode: CVMCPU_MEMSPEC_IMMEDIATE_OFFSET: */
    CVMInt32       offsetValue;

    /* Address mode: CVMCPU_MEMSPEC_REG_OFFSET: */
    CVMRMResource *offsetReg;
    CVMInt32       shiftOpcode;
    CVMInt32       shiftAmount;
};

typedef CVMUint32 CVMCPUMemSpecToken;

/**************************************************************
 * CPU MemSpec and associated types
 **************************************************************/

/* MemSpec private definitions: =========================================== */

/*
 * These are the address-mode computation bits used for modes 2 and 3.
 * the P, U, and W bits (pre/post index, offset add/subtract, and write back)
 * are common and are ORed directly into the instruction. The imm/reg offset
 * indicator bit has to be steered based on opcode. And of course the
 * representation of an immediate value is opcode dependent as well.
 *
 * Be careful of the U bit: for an immediate offset it is NOT the same
 * as a sign bit. Default needs to be U bit set.
 * 
 * Be careful of the P bit: for the usual operations, you want to
 * preindex. Failing to do so will compute the wrong address AND
 * cause the base register to be updated. Default needs to be P bit set.
 */
#define ARM_LOADSTORE_PREINDEX	0x01000000	/* P bit */
#define ARM_LOADSTORE_ADDOFFSET	0x00800000	/* U bit */
#define ARM_LOADSTORE_WRITEBACK 0x00200000	/* W bit */ 
#define ARM_LOADSTORE_IMMEDIATE_OFFSET 0
#define ARM_LOADSTORE_REGISTER_OFFSET (1 << 25)
#define ARM_LOADSTORE_MODE3_IMMEDIATE_OFFSET (1 << 22)

/* The common combinations: reg+reg addressing, reg+imm addressing */
#define ARM_MEMSPEC_IMMEDIATE_OFFSET \
    (ARM_LOADSTORE_PREINDEX | ARM_LOADSTORE_ADDOFFSET | \
    ARM_LOADSTORE_IMMEDIATE_OFFSET)

#define ARM_MEMSPEC_REG_OFFSET \
    (ARM_LOADSTORE_PREINDEX | ARM_LOADSTORE_ADDOFFSET | \
    ARM_LOADSTORE_REGISTER_OFFSET)

/*
 * How to use the load/store word instructions to access a stack:
 * These assume that stack grows + and that the stack pointer is
 * addressing the EMPTY cell after the top. Thus post-increment and
 * pre-decrement are what you want.
 */
#define ARM_MEMSPEC_POSTINCREMENT_IMMEDIATE_OFFSET \
	(ARM_LOADSTORE_IMMEDIATE_OFFSET | ARM_LOADSTORE_ADDOFFSET)

#define ARM_MEMSPEC_PREDECREMENT_IMMEDIATE_OFFSET \
	(ARM_LOADSTORE_PREINDEX | ARM_LOADSTORE_IMMEDIATE_OFFSET | \
	ARM_LOADSTORE_WRITEBACK)

/**************************************************************
 * CPU C Call convention abstraction - The following are prototypes of calling
 * convention support functions required by the RISC emitter porting layer.
 **************************************************************/
typedef struct CVMCPUCallContext CVMCPUCallContext;
struct CVMCPUCallContext
{
    CVMRMResource *reservedRes;
};

#define CVMCPU_HAVE_PLATFORM_SPECIFIC_C_CALL_CONVENTION

#ifdef CVMJIT_TRAP_BASED_GC_CHECKS
#define CVMCPU_GCTRAP_INSTRUCTION \
    (CVMCPU_COND_AL << 28 | CVMCPU_LDR32_OPCODE | \
     ARM_LOADSTORE_PREINDEX  | \
     CVMCPU_GC_REG << 16 | CVMCPU_GC_REG << 12)
#define CVMCPU_GCTRAP_INSTRUCTION_MASK ~0x00800fff
#endif

#endif /* _INCLUDED_ARM_JITRISCEMITTERDEFS_CPU_H */