jitriscemitterdefs_cpu.h

This is a resource based on j2me embedded,if you dont understand,you can connection with me .

/*
 * @(#)jitriscemitterdefs_cpu.h	1.27 06/10/10
 *
 * Copyright  1990-2008 Sun Microsystems, Inc. All Rights Reserved.  
 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER  
 *   
 * This program is free software; you can redistribute it and/or  
 * modify it under the terms of the GNU General Public License version  
 * 2 only, as published by the Free Software Foundation.   
 *   
 * This program is distributed in the hope that it will be useful, but  
 * WITHOUT ANY WARRANTY; without even the implied warranty of  
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU  
 * General Public License version 2 for more details (a copy is  
 * included at /legal/license.txt).   
 *   
 * You should have received a copy of the GNU General Public License  
 * version 2 along with this work; if not, write to the Free Software  
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  
 * 02110-1301 USA   
 *   
 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa  
 * Clara, CA 95054 or visit www.sun.com if you need additional  
 * information or have any questions. 
 *
 */

#ifndef _INCLUDED_ARM_JITRISCEMITTERDEFS_CPU_H
#define _INCLUDED_ARM_JITRISCEMITTERDEFS_CPU_H

#include "javavm/include/jit/jitrisc_cpu.h"

/*
 * This file defines all of the emitter types and option definitions that
 * in a platform indendent way to be used by the common RISC jit back end.
 * The exported symbols are prefixed with CVMCPU_.  Other symbols should be
 * considered private to the ARM specific parts of the jit, including those
 * with the CVMARM_ prefix.
 *
 * This file should be included at the top of jitriscemitter.h.
 */

/**************************************************************
 * CPU condition codes - The following are definition of the condition
 * codes that are required by the RISC emitter porting layer.
 **************************************************************/

typedef enum CVMCPUCondCode {
    CVMCPU_COND_EQ = 0,     /* Do when equal */
    CVMCPU_COND_NE = 1,     /* Do when NOT equal */
    CVMCPU_COND_MI = 4,     /* Do when has minus / negative */
    CVMCPU_COND_PL = 5,     /* Do when has plus / positive or zero */
    CVMCPU_COND_OV = 6,     /* Do when overflowed */
    CVMCPU_COND_NO = 7,     /* Do when NOT overflowed */
    CVMCPU_COND_LT = 11,    /* Do when signed less than */
    CVMCPU_COND_GT = 12,    /* Do when signed greater than */
    CVMCPU_COND_LE = 13,    /* Do when signed less than or equal */
    CVMCPU_COND_GE = 10,    /* Do when signed greater than or equal */
    CVMCPU_COND_LO = 3,     /* Do when lower / unsigned less than */
    CVMCPU_COND_HI = 8,     /* Do when higher / unsigned greater than */
    CVMCPU_COND_LS = 9,     /* Do when lower or same / is unsigned <= */
    CVMCPU_COND_HS = 2,     /* Do when higher or same / is unsigned >= */
    CVMCPU_COND_AL = 14,    /* Do always */
    CVMCPU_COND_NV = 15     /* Do never */

#ifdef CVM_JIT_USE_FP_HARDWARE
    /*
     * Floating-point condition codes are necessary for using floating
     * point hardware. They are in the same set as int condition codes,
     * but easily distinguishable from them.
     *
     * Remember that by default unordered should be treated as
     * greater than. If the UNORDERED_LT flag is set, then unordered
     * is treated as less than.
     */
#define CVMCPU_COND_UNORDERED_LT	32
    ,
    CVMCPU_COND_FEQ = CVMCPU_COND_EQ, /* Do when equal */
    CVMCPU_COND_FNE = CVMCPU_COND_NE, /* Do when NOT equal */
    CVMCPU_COND_FLT = CVMCPU_COND_LT, /* Do when less than */
    CVMCPU_COND_FGT = CVMCPU_COND_GT, /* Do when greater than */
    CVMCPU_COND_FLE = CVMCPU_COND_LE, /* Do when less than or equal */
    CVMCPU_COND_FGE = CVMCPU_COND_GE  /* Do when greater than or equal */
#endif /* CVM_JIT_USE_FP_HARDWARE */
    
} CVMCPUCondCode;

/**************************************************************
 * CPU Opcodes - The following are definition of opcode encodings
 * that are required by the RISC emitter porting layer.  Where
 * actual opcodes do not exists, pseudo opcodes are substituted.
 **************************************************************/

#define CVMCPU_NOP_INSTRUCTION     0xe1a00000  /* mov r0, r0 */

#ifdef IAI_CODE_SCHEDULER_SCORE_BOARD
#define CVMCPU_NOP2_INSTRUCTION    0xe1a01001  /* mov r1, r1 */
#define CVMCPU_NOP3_INSTRUCTION    0xe1a02002  /* mov r2, r2 */
#endif /* IAI_CODE_SCHEDULER_SCORE_BOARD */

/* Memory Reference opcodes: */
#define CVMCPU_LDR64_OPCODE     0x00000000  /* Load signed 64 bit value. */
#define CVMCPU_STR64_OPCODE     0x00000001  /* Store 64 bit value. */
#define CVMCPU_LDR32_OPCODE     0x04100000  /* Load signed 32 bit value. */
#define CVMCPU_STR32_OPCODE     0x04000000  /* Store 32 bit value. */
#define CVMCPU_STR8_OPCODE      0x04400000  /* Store 8 bit value. */

/* The following are ARMv4 only, and use addressing mode 3 */
#define CVMCPU_LDR16U_OPCODE    0x005000b0  /* Load unsigned 16 bit value. */
#define CVMCPU_LDR16_OPCODE     0x005000f0  /* Load signed 16 bit value. */
#define CVMCPU_STR16_OPCODE     0x004000b0  /* Store 16 bit value. */
#define CVMCPU_LDR8U_OPCODE     0x04500000  /* Load unsigned 8 bit value. */
#define CVMCPU_LDR8_OPCODE      0x005000d0  /* Load signed 8 bit value. */

/* Floating Point Mememory reference opcodes using addressing mode 5 */
#define CVMCPU_FLDR32_OPCODE 0x0d100a00 /* Load float 32 bit value */
#define CVMCPU_FLDR64_OPCODE 0x0d100b00 /* Load float 64 bit value */
#define CVMCPU_FSTR32_OPCODE 0x0d000a00 /* Store float 32 bit value */
#define CVMCPU_FSTR64_OPCODE 0x0d000b00 /* Store float 64 bit value */

/* Floating-point Memory reference opcodes: */
/* Used only within ARM-specific code generation */
#define CVMARM_FLDRM32_OPCODE 0x0c100a00 /* Load multiple float 32 bit value */
#define CVMARM_FLDRM64_OPCODE 0x0c100b00 /* Load multiple float 64 bit value */
#define CVMARM_FSTRM32_OPCODE 0x0c000a00 /* Store multiple float 32 bit value */
#define CVMARM_FSTRM64_OPCODE 0x0c000b00 /* Store multiple float 64 bit value */


/* 32 bit ALU opcodes: */
#define CVMCPU_MOV_OPCODE   (0x1a << 20) /* reg32 = aluRhs32. */
#define CVMCPU_NEG_OPCODE   0x00000003   /* reg32 = -reg32. */
#define CVMCPU_NOT_OPCODE   0x00000004   /* reg32 = (reg32 == 0)?1:0. */
#define CVMCPU_INT2BIT_OPCODE 0x00000005 /* reg32 = (reg32 != 0)?1:0. */
#define CVMCPU_ADD_OPCODE   (0x08 << 20) /* reg32 = reg32 + aluRhs32. */
#define CVMCPU_SUB_OPCODE   (0x04 << 20) /* reg32 = reg32 - aluRhs32. */
#define CVMCPU_AND_OPCODE   (0x00 << 20) /* reg32 = reg32 AND aluRhs32. */
#define CVMCPU_OR_OPCODE    (0x18 << 20) /* reg32 = reg32 OR aluRhs32. */
#define CVMCPU_XOR_OPCODE   (0x02 << 20) /* reg32 = reg32 XOR aluRhs32. */
#define CVMCPU_BIC_OPCODE   (0x1c << 20) /* reg32 = reg32 AND ~aluRhs32. */
#define CVMARM_RSB_OPCODE   (0x06 << 20) /* reg32 = aluRhs32 - reg32. */

/* Mode 1 and 2 shift ops: */
#define CVMCPU_SLL_OPCODE       (0 << 5)
#define CVMCPU_SRL_OPCODE       (1 << 5)
#define CVMCPU_SRA_OPCODE       (2 << 5)
#define CVMARM_NOSHIFT_OPCODE   CVMCPU_SLL_OPCODE

#define CVMARM_MLA_OPCODE   0x00200090   /* reg32 = reg32 + (reg32 * reg32) */
#define CVMCPU_MULL_OPCODE  0x00000090   /* reg32 = LO32(reg32 * reg32). */
#define CVMCPU_MULH_OPCODE  0x00C00090   /* reg32 = HI32(reg32 * reg32). */
#define CVMCPU_CMP_OPCODE   (0x15 << 20) /* cmp reg32, aluRhs32 => set cc. */
#define CVMCPU_CMN_OPCODE   (0x17 << 20) /* cmp reg32, -aluRhs32 => set cc. */

#ifdef CVMJIT_SIMPLE_SYNC_METHODS
#if CVM_FASTLOCK_TYPE == CVM_FASTLOCK_MICROLOCK && \
    CVM_MICROLOCK_TYPE == CVM_MICROLOCK_SWAP_SPINLOCK
/* Atomic swap opcode */
#define CVMARM_SWP_OPCODE  0x01000090
#endif
#endif

/* 32-bit floating point opcodes: */
#define CVMCPU_FADD_OPCODE ((0x1c << 23) | (0x3 << 20) | (0xa << 8) \
                          | (0x0 << 6))
#define CVMCPU_FSUB_OPCODE ((0x1c << 23) | (0x3 << 20) | (0xa << 8) \
                          | (0x1 << 6))
#define CVMCPU_FMUL_OPCODE ((0x1c << 23) | (0x2 << 20) | (0xa << 8) \
                          | (0x0 << 6))
#define CVMCPU_FDIV_OPCODE ((0x1d << 23) | (0x0 << 20) | (0xa << 8) \
                          | (0x0 << 6))
#define CVMCPU_FCMP_OPCODE ((0x1d << 23) | (0x3 << 20) | (0x4 << 16) \
                          | (0xa << 8) | (0x0 << 7) | (0x1 << 6))
#define CVMCPU_FNEG_OPCODE ((0x1d << 23) | (0x3 << 20) | (0x1 << 16) \
                          | (0xa << 8) | (0x0 << 7) | (0x1 << 6))
/* Floating-point opcode to move within floating point registers: */
#define CVMCPU_FMOV_OPCODE ((0x1d << 23) | (0x3 << 20) | (0xa << 8) \
                          | (0x0 << 7) | (0x1 << 6)) /* FCPYS */

/* 64-bit floating point opcodes: */
#define CVMCPU_DADD_OPCODE ((0x1c << 23) | (0x3 << 20) | (0xb << 8) \
                          | (0x0 << 6))
#define CVMCPU_DSUB_OPCODE ((0x1c << 23) | (0x3 << 20) | (0xb << 8) \
                          | (0x1 << 6))   
#define CVMCPU_DMUL_OPCODE ((0x1c << 23) | (0x2 << 20) | (0xb << 8) \
                          | (0x0 << 6))   
#define CVMCPU_DDIV_OPCODE ((0x1d << 23) | (0x0 << 20) | (0xb << 8) \
                          | (0x0 << 6))   
#define CVMCPU_DCMP_OPCODE ((0x1d << 23) | (0x3 << 20) | (0x4 << 16) \
                          | (0xb << 8) | (0x0 << 7) | (0x1 << 6))
#define CVMCPU_DNEG_OPCODE ((0x1d << 23) | (0x3 << 20) | (0x1 << 16) \
                          | (0xb << 8) | (0x0 << 7) | (0x1 << 6))
/* Floating-point opcode to move within floating point registers: */
#define CVMCPU_DMOV_OPCODE ((0x1d << 23) | (0x3 << 20) | (0xb << 8) \
                          | (0x0 << 7) | (0x1 << 6)) /* FCPYD */


/* Floating-point conversion opcodes: */
/* Used only within ARM-specific code generation */
#define CVMARM_I2F_OPCODE ((0x1d << 23) | (0x3 << 20) | (0x8 << 16) \
                         | (0xa << 8) | (0x1 << 7) | (0x1 << 6))