jitriscemitter_cpu.h

This is a resource based on j2me embedded,if you dont understand,you can connection with me .

/*
 * @(#)jitriscemitter_cpu.h	1.97 06/10/10
 *
 * Copyright  1990-2008 Sun Microsystems, Inc. All Rights Reserved.  
 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER  
 *   
 * This program is free software; you can redistribute it and/or  
 * modify it under the terms of the GNU General Public License version  
 * 2 only, as published by the Free Software Foundation.   
 *   
 * This program is distributed in the hope that it will be useful, but  
 * WITHOUT ANY WARRANTY; without even the implied warranty of  
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU  
 * General Public License version 2 for more details (a copy is  
 * included at /legal/license.txt).   
 *   
 * You should have received a copy of the GNU General Public License  
 * version 2 along with this work; if not, write to the Free Software  
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  
 * 02110-1301 USA   
 *   
 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa  
 * Clara, CA 95054 or visit www.sun.com if you need additional  
 * information or have any questions. 
 *
 */

#ifndef _INCLUDED_ARM_JITRISCEMITTER_CPU_H
#define _INCLUDED_ARM_JITRISCEMITTER_CPU_H

/*
 * This file #defines all of the emitter function prototypes and macros that
 * shared parts use in a platform indendent way in RISC ports of the jit back
 * end. The exported functions and macros are prefixed with CVMCPU_.  Other
 * functions and macros should be considered private to the ARM specific parts
 * of the jit, including those with the CVMARM_ prefix.
 */

/**********************************************************************
 * Some very ARM-specific bits of code generation.
 * Our stack layout and the names of the registers we're going to use
 * to access it:
 *
 *	+----------------------
 *	| Java local 0
 *	+----------------------
 *	...
 *	+----------------------
 *	| Java local n
 *	+----------------------
 * JFP->| control information here
 *	| of some size...
 *	+----------------------
 *	| Java temp 0	( code generation allocated )
 *	+----------------------
 *	...
 *	+----------------------
 *	| Java temp n	( code generation allocated )
 *	+----------------------
 * JSP->| Outgoing Java parameters.
 *	+----------------------
 *
 * Java locals and temps accessed via JFP,
 * JSP  used to access only the stack top.
 *
 * In truth, we really only need JSP, since the offsets of everything
 * else are known at compilation of each instruction. But we could never
 * debug the resulting code! That would not be desirable.
 */

/**************************************************************
 * CPU ALURhs and associated types - The following are function
 * prototypes and macros for the ALURhs abstraction required by
 * the RISC emitter porting layer.
 **************************************************************/

/* ALURhs constructors and query APIs: ==================================== */

/* Purpose: Constructs an ALURhs to represent a register shifted by a
            constant. */
CVMCPUALURhs*
CVMARMalurhsNewShiftByConstant(CVMJITCompilationContext*, int shiftop,
                               CVMRMResource*, CVMInt32 shiftval);

/* Purpose: Constructs an ALURhs to represent a register shifted by another
            register. */
CVMCPUALURhs*
CVMARMalurhsNewShiftByReg(CVMJITCompilationContext*, int shiftop,
                          CVMRMResource*, CVMRMResource*);

#define CVMCPUalurhsNewRegister(con, rp) \
    CVMARMalurhsNewShiftByConstant(con, CVMARM_NOSHIFT_OPCODE, rp, 0)

#define CVMCPUalurhsIsEncodableAsImmediate(opcode, constValue) \
    (((CVMUint32)(constValue) <= 255) || \
     CVMARMmode1EncodeImmediate((CVMUint32)(constValue), NULL, NULL))

#define CVMCPUalurhsIsConstant(aluRhs) \
    ((aluRhs)->type == CVMARM_ALURHS_CONSTANT)

#define CVMCPUalurhsGetConstantValue(aluRhs)    ((aluRhs)->constValue)

/* ALURhs token encoder APIs: ============================================= */

/* Purpose: Gets the token for the ALURhs value for use in the instruction
            emitters. */
CVMCPUALURhsToken
CVMARMalurhsGetToken(CVMJITCompilationContext* con,
		     const CVMCPUALURhs *aluRhs);

#define CVMCPUalurhsGetToken(con, aluRhs)   \
     ((void)(con), CVMARMalurhsGetToken(con, aluRhs))

/* Purpose: Encodes an CVMCPUALURhsToken for the specified arguments. */
/* NOTE: This function is private to the ARM implementation and can only be
         called from the shared implementation via the CVMCPUxxx macros
         below. */
CVMCPUALURhsToken
CVMARMalurhsEncodeToken(CVMJITCompilationContext* con,
			CVMARMALURhsType type, int constValue,
                        int shiftOp, int r1RegID, int r2RegID);

/* Purpose: Encodes a CVMCPUALURhsToken for the specified constant value. */
#define CVMARMalurhsEncodeConstantToken(con, constValue) \
    (((CVMUint32)(constValue) <= 255) ? \
     (CVMARM_MODE1_CONSTANT | (constValue)) : \
      CVMARMalurhsEncodeToken(con, CVMARM_ALURHS_CONSTANT, (constValue), \
         CVMARM_NOSHIFT_OPCODE, CVMCPU_INVALID_REG, CVMCPU_INVALID_REG))

#ifndef IAI_CODE_SCHEDULER_SCORE_BOARD

/* Purpose: Encodes a CVMCPUALURhsToken for the specified register ID. */
#define CVMARMalurhsEncodeRegisterToken(con, regID) \
     (CVMARM_MODE1_SHIFT_CONSTANT | CVMARM_NOSHIFT_OPCODE | (regID))

/* Purpose: Encodes a ShiftByConstant CVMCPUALURhsToken. */
#define CVMARMalurhsEncodeShiftByConstantToken(con, \
					       regID, shiftOp, shiftAmount) \
    (((shiftAmount) == 0) ? \
     (CVMARM_MODE1_SHIFT_CONSTANT | (regID) | CVMCPU_SLL_OPCODE | 0) : \
     (CVMARM_MODE1_SHIFT_CONSTANT | (regID) | (shiftOp) | (shiftAmount)<<7))

#else  /* IAI_CODE_SCHEDULER_SCORE_BOARD */

/* Purpose: Encodes a CVMCPUALURhsToken for the specified register ID. */
#define CVMARMalurhsEncodeRegisterToken(con, regID) \
     (CVMJITcsPushSourceRegister(con, regID),\
      CVMARM_MODE1_SHIFT_CONSTANT | CVMARM_NOSHIFT_OPCODE | (regID))

/* Purpose: Encodes a ShiftByConstant CVMCPUALURhsToken. */
#define CVMARMalurhsEncodeShiftByConstantToken(con, \
					       regID, shiftOp, shiftAmount) \
    (CVMJITcsPushSourceRegister(con, regID),\
     ((shiftAmount) == 0) ? \
     (CVMARM_MODE1_SHIFT_CONSTANT | (regID) | CVMCPU_SLL_OPCODE | 0) : \
     (CVMARM_MODE1_SHIFT_CONSTANT | (regID) | (shiftOp) | (shiftAmount)<<7))

#endif /* IAI_CODE_SCHEDULER_SCORE_BOARD */

/**************************************************************
 * CPU MemSpec and associated types - The following are function
 * prototypes and macros for the MemSpec abstraction required by
 * the RISC emitter porting layer.
 **************************************************************/

/* MemSpec query APIs: ==================================================== */

#define CVMARMisMode2Instruction(opcode) ((opcode >> 26) == 0x1)

#define CVMCPUmemspecIsEncodableAsImmediate(value) \
    ((-0xfff <= ((CVMInt32)(value))) && (((CVMInt32)(value)) <= 0xfff))

#define CVMCPUmemspecIsEncodableAsOpcodeSpecificImmediate(opcode, value) \
    (CVMARMisMode2Instruction(opcode) ? \
     CVMCPUmemspecIsEncodableAsImmediate(value) : ((value) <= 255))

#define CVMARMisMode5Instruction(opcode) ((opcode >> 26) == 0x3)

/* MemSpec token encoder APIs: ============================================ */

/* Purpose: Encodes a CVMCPUMemSpecToken from the specified memSpec. */
CVMCPUMemSpecToken
CVMARMmemspecGetToken(CVMJITCompilationContext* con,
		      const CVMCPUMemSpec *memSpec);

#define CVMCPUmemspecGetToken(con, memSpec) \
    ((void)(con), CVMARMmemspecGetToken(con, memSpec))

/* NOTE: The CVMCPUMemSpecToken is encoded as:
        bits 31 - 16:   signed offset or regID;
        bits 15:        unused;
        bits 14 - 13:   shiftOpcode;
        bits 12 - 8:    shiftAmount;
        bits 7 - 0:     memSpec type;
*/

#define CVMARMmemspecEncodeToken(type, offset, shiftOp, shiftImm) \
    (CVMassert((CVMUint32)(shiftImm) <= 31), \
     ((((offset) & 0xffff) << 16) | (((shiftOp) | (shiftImm)) << 8) | (type)))

#define CVMCPUmemspecEncodeImmediateToken(con, offset) \
    ((void)(con), CVMassert(CVMCPUmemspecIsEncodableAsImmediate(offset)), \
      CVMARMmemspecEncodeToken(CVMCPU_MEMSPEC_IMMEDIATE_OFFSET, \
                        (offset), CVMARM_NOSHIFT_OPCODE, 0))

#define CVMCPUmemspecEncodePostIncrementImmediateToken(con, increment) \
    ((void)(con), CVMassert(CVMCPUmemspecIsEncodableAsImmediate(increment)), \
     CVMARMmemspecEncodeToken(CVMCPU_MEMSPEC_POSTINCREMENT_IMMEDIATE_OFFSET, \
                              (increment), CVMARM_NOSHIFT_OPCODE, 0))

#define CVMCPUmemspecEncodePreDecrementImmediateToken(con, decrement) \
    ((void)(con), CVMassert(CVMCPUmemspecIsEncodableAsImmediate(decrement)), \
     CVMARMmemspecEncodeToken(CVMCPU_MEMSPEC_PREDECREMENT_IMMEDIATE_OFFSET, \
                              (decrement), CVMARM_NOSHIFT_OPCODE, 0))

/**************************************************************
 * CPU code emitters - The following are prototypes of code
 * emitters required by the RISC emitter porting layer.
 **************************************************************/

/* ===== MemoryReference Emitter APIs ===================================== */

#define CVMCPUemitMemoryReferencePCRelative(con, opcode, destRegID, offset) \
    CVMCPUemitMemoryReferenceImmediate((con), (opcode), \
        (destRegID), CVMARM_PC, (offset - 8))

#define CVMCPUemitMemoryReferenceImmediate(con, opcode, destreg, basereg, \
                                           immOffset) \
    CVMCPUemitMemoryReferenceImmediateConditional((con), (opcode), \
        (destreg), (basereg), (immOffset), CVMCPU_COND_AL)

#define CVMCPUemitMemoryReference(con, opcode, destreg, basereg, memSpecToken)\
    CVMCPUemitMemoryReferenceConditional((con), (opcode), \