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📄 jit.h

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#define CVMJIT_PATCH_BASED_GC_CHECKS/* * IAI-20: * For inlined virtual method invocation, use class guard test to  * replace the original method guard test; move method guard test * into out-of-line block to guard those failed in class guard test. * * By default this is enabled. */#define IAI_VIRTUAL_INLINE_CB_TEST#ifndef _ASM/****************************************************************** * Purpose: Initialized the target specific compiler back-end. * Supplied by the target. */extern CVMBoolCVMJITinitCompilerBackEnd(void);/* * Purpose: Destroys the target specific compiler back-end. */extern voidCVMJITdestroyCompilerBackEnd(void);#ifdef CVM_JIT_PATCHED_METHOD_INVOCATIONS/* Purpose: back-end PMI initialization. */extern CVMBoolCVMJITPMIinitBackEnd(void);#endif/****************************************************************** * The following two code cache functions are called if  * the macro CVMJIT_HAVE_PLATFORM_SPECIFIC_ALLOC_FREE_CODECACHE * is defined. They must be supplied by the target port. * Otherwise, malloc is used. *//* * Purpose: Allocate the code cache. */void *CVMJITallocCodeCache(CVMSize *size);/* * Purpose: Free the code cache. */voidCVMJITfreeCodeCache(void *start);/****************************************************************** * JIT AOT API's. Only need to be implemented if CVM_AOT is  * #define'd. *//* Don't use fixed address for AOT codecache by default. */#undef CVMAOT_USE_FIXED_ADDRESS/* Purpose: Find AOT code from the persistent storage. Initialize *          following AOT related global variables: *              jgs->codeCacheAOTStart *              jgs->codeCacheAOTEnd *              jgs->codeCacheAOTCodeExist *          The return value is the size of the AOT code. *          If there is no existing AOT code, allocate a consecutive *          code cache for both AOT and JIT compilation. */extern CVMInt32CVMfindAOTCode();/*  * The compiled code below the codeCacheDecompileStart will be saved * into persistent storage if there is no previouse saved AOT code,  * and will be reloaded next time. * On linux, for example we write the AOT code size as the first word. * The saved code cache looks like the following: * *  ------------------------------------------------------ *  |size|                                               | *  |-----                                               | *  |                                                    | *  |                 compiled code                      | *  .                                                    . *  .                                                    . *  .                                                    . *  |                                                    | *  ------------------------------------------------------ */extern voidCVMJITcodeCachePersist();/******************************************************************//* * Code generation entry point. * Supplied by the RISC layer for RISC ports */extern voidCVMJITcompileGenerateCode(CVMJITCompilationContext* con);/* * Flush I & D caches for given range after writing compiled code. * Must be defined by the target. NOTE: when flushing after patching * a single instruction, "begin" must be the actual address of the * patched instruction. No rounding (such as to the cache line * boundary) should be done. */extern voidCVMJITflushCache(void* begin, void* end);/* Purpose: Massage the compiled PC.  This is used in the mapping of a compiled            PC to Java Bytecode PC.  The massaging is necessary because            compiled PCs point to the return address from a method call as            opposed to the caller's PC as is the convention for Java PCs.	    Supplied by the RISC layer for RISC ports */extern CVMUint8 *CVMJITmassageCompiledPC(CVMUint8 *compiledPC, CVMUint8 *startPC);/****************************************************************** * JIT profiling API's * If the target is a Posix system, these can be provided by the POSIX layer. *//* Return how big the profiling buffer needs to be */CVMUint32CVMJITprofileBufferSize();/* enable profiling */voidCVMJITprofileEnable();/* disable profiling */voidCVMJITprofileDisable();/* return code pointer for next region profiled */CVMUint8*CVMJITprofileGetNextProfiledRegion(CVMUint8* regionPtr);/* return sample count for specified region */CVMUint32CVMJITprofileGetSampleCount(CVMUint8* regionPtr);/* number of samples taken per second *//* CVMJIT_PROFILE_SAMPLES_PER_SECOND *//****************************************************************** * GC CheckPoints APIs. * * These APIs only need to be implemented if CVMJIT_PATCH_BASED_GC_CHECKS * or CVMJIT_TRAP_BASED_GC_CHECKS are #define'd. The are tasked with * enabling and disabling gc rendezvous points (checkpoints) in compiled * code. */extern voidCVMJITenableRendezvousCalls(CVMExecEnv* ee);extern voidCVMJITdisableRendezvousCalls(CVMExecEnv* ee);extern voidCVMJITenableRendezvousCallsTrapbased(CVMExecEnv* ee);extern voidCVMJITdisableRendezvousCallsTrapbased(CVMExecEnv* ee);/****************************************************************** * Runtime routines supplied by the target: * * Enter a compiled method from the interpreter loop. * CVMMethodBlock* return value allows * the compiled code to 'return' to the interpreter for execution * of an interpreted method. */extern CVMMethodBlock*CVMJITgoNative(CVMObject* exceptionObject, CVMExecEnv* ee,	       CVMCompiledFrame* jfp, void* pc);/* * Exit a compiled method and return to the interpreter loop. * Returns NULL to the caller of CVMJITgoNative. * Used in exception handling. */extern voidCVMJITexitNative(CVMCCExecEnv* ccee);/* * Fixup up uninitialized fields in compiled frames * In compiled code, we don't always keep all the bits in * the stack frame perfectly up to date. This reduces overhead, * but requires use of this function when correctness does matter. */extern voidCVMJITfixupFrames(CVMFrame *);/****************************************************************** * Used and supplied by the RISC layer for RISC ports: * Special backend actions to be done at the beginning and end of each * codegen rule. Usually only enabled when debugging. * Not needed when not using JCS-based code generation. */extern voidCVMJITdoStartOfCodegenRuleAction(CVMJITCompilationContext *con, int ruleno,                                 const char *description,                                 CVMJITIRNode* node);extern voidCVMJITdoEndOfCodegenRuleAction(CVMJITCompilationContext *con);/****************************************************************** * Compilation routines supplied by the target: * * CVMJITcanReachAddress - Check if toPC can be reached by an * instruction at fromPC using the specified addressing mode. If * needMargin is true, then a margin of safety is added (usually the * allowed offset range is cut in half). * Also used for determining when to dump a constant pool. */extern CVMBoolCVMJITcanReachAddress(CVMJITCompilationContext* con,		      int fromPC, int toPC,		      CVMJITAddressMode mode, CVMBool needMargin);/* * CVMJITfixupAddress - change the instruction to reference the specified * targetLogicalAddress. */extern voidCVMJITfixupAddress(CVMJITCompilationContext* con,		   int instructionLogicalAddress,		   int targetLogicalAddress,		   CVMJITAddressMode instructionAddressMode);#ifdef IAI_CACHEDCONSTANT/* * CVMJITemitLoadConstantAddress - Emit instruction(s) to load the address * of a constant pool constant into a platform defined register. */extern voidCVMJITemitLoadConstantAddress(CVMJITCompilationContext* con,			      int targetLogicalAddress);#endif/* * Emit a 32 bit value (aka .word). * Supplied by the target. * This is used by jitconstantpool manager, which is independent * of the RISC layer, as well as a number of places in the RISC layer. * Other emitters that are used only within the RISC * layer are declared in a different file. */extern voidCVMJITemitWord(CVMJITCompilationContext *con, CVMInt32 const32);#ifdef CVM_JIT_PATCHED_METHOD_INVOCATIONS/* * Patch CPU specific branch bits. *  * This is used for the patched method invocations implementation. * The implementation of this method will patch the actual * bits of the branch instruction at instr_addr, so that * the branch will now point to the new offset from instr_addr. */extern void CVMCPUpatchBranchInstruction(int offset, CVMUint8* instr_addr);#endif/* * More porting layer constants are defined in ccm.h. See details there. */#include "javavm/include/porting/jit/ccm.h"#endif /* _ASM */#ifdef CVM_HDR_JIT_JIT_H#include CVM_HDR_JIT_JIT_H#endif#ifdef CVMJIT_INTRINSICS/* The following must come after CVM_HDR_JIT_JIT_H is included so that the * target can override it: */#ifndef CVMJITintrinsicsList#define CVMJITintrinsicsList CVMJITdefaultIntrinsicsList#endif#endif /* CVMJIT_INTRINSICS */#endif /* _INCLUDED_PORTING_JIT_JIT_H */

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