jitfloatgrammarrules.jcs

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//
// @(#)jitfloatgrammarrules.jcs	1.7 06/10/23
// 
// Portions Copyright  2000-2008 Sun Microsystems, Inc. All Rights
// Reserved.  Use is subject to license terms.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER
// 
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License version
// 2 only, as published by the Free Software Foundation.
// 
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License version 2 for more details (a copy is
// included at /legal/license.txt).
// 
// You should have received a copy of the GNU General Public License
// version 2 along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
// 02110-1301 USA
// 
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
// Clara, CA 95054 or visit www.sun.com if you need additional
// information or have any questions.
//

// Optional floating-point grammar rules for processors with
// floating-point hardware.
//
// These rules will only be used if `CVM_JIT_USE_FP_HARDWARE' is
// defined.

%unary FIDENT
%unary DIDENT
%unary FDEFINE
%unary DDEFINE
%leaf FUSED
%leaf DUSED
%unary FENDINLINING
%unary DENDINLINING
%binary FSEQUENCE_R
%binary DSEQUENCE_R
%binary FSEQUENCE_L
%binary DSEQUENCE_L

%binary INVOKE32F	// return type is float32
%binary INVOKE64F       // return type is float64

//
// The following nodes are to mark the end of the inlining of a method
// The three cases are: the method returns nothing, a 32-bit value, and
// a 64-bit value.
//
freg32: FENDINLINING freg32 : 0 : : : : {
    endInlining(con, $$);
    passLastEvaluated(con, CVMRM_FP_REGS(con), $$);
};

freg64: DENDINLINING freg64 : 0 : : : : {
    endInlining(con, $$);
    passLastEvaluated(con, CVMRM_FP_REGS(con), $$);
};

//
//
// Sequences:
//
freg32: FSEQUENCE_R effect freg32 : 0 : :
	SEQUENCE_R_INHERITANCE($$, CVMRM_FP_REGS(con)); : : {
    passLastEvaluated(con, CVMRM_FP_REGS(con), $$);
};

freg64: DSEQUENCE_R effect freg64 : 0 : :
	SEQUENCE_R_INHERITANCE($$, CVMRM_FP_REGS(con)); : : {
    passLastEvaluated(con, CVMRM_FP_REGS(con), $$);
};

//
// "L" Sequences:
//
freg32: FSEQUENCE_L freg32 effect : 0 : :
	SEQUENCE_L_INHERITANCE($$, CVMRM_FP_REGS(con)); : : {
    passLastEvaluated(con, CVMRM_FP_REGS(con), $$);
};

freg64: DSEQUENCE_L freg64 effect : 0 : :
        SEQUENCE_L_INHERITANCE($$, CVMRM_FP_REGS(con)); : : {
    passLastEvaluated(con, CVMRM_FP_REGS(con), $$);
};

// Purpose: value32 = FETCH32(STATIC32(staticFieldSpec))
freg32: FETCH32 STATIC32 memSpec : 20 : : : : {
   CVMJITprintCodegenComment(("Do getstatic:"));
        CVMJITaddCodegenComment((con,
            "value{I|F|O} = getstatic(staticFieldAddr);"));
        getStaticField(con, CVMRM_FP_REGS(con),
		       $$, GET_FLOAT_REGISTER_GOALS, CVMCPU_FLDR32_OPCODE, 1);
    };

// Purpose: value = FETCH32(FIELDREF32(obj,fieldOffset))
freg32: FETCH32 FIELDREF32 regObj memSpec : 10 :
    GETFIELD_SYNTHESIS(con, $$); : GETFIELD_INHERITANCE(con, $$); : : {
        CVMJITprintCodegenComment(("Do getfield:"));
        CVMJITaddCodegenComment((con, "value{I|F}"));
        fetchField(con, CVMRM_FP_REGS(con), $$,
		   GET_FLOAT_REGISTER_GOALS, CVMCPU_FLDR32_OPCODE, 1);
    };

// Purpose: value64 = FETCH64(STATIC64(staticFieldSpec))
freg64: FETCH64 STATIC64 memSpec : 20 : : : : {
        CVMJITprintCodegenComment(("Do getstatic:"));
        CVMJITaddCodegenComment((con,
            "value{D} = getstatic(staticFieldAddr);"));
        getStaticField(con, CVMRM_FP_REGS(con),
		       $$, GET_FLOAT_REGISTER_GOALS, CVMCPU_FLDR64_OPCODE, 2);
    };

// Purpose: value = FETCH64(FIELDREF64(obj,fieldOffset))
freg64: FETCH64 FIELDREF64 regObj memSpec : 10 :
    GETFIELD_SYNTHESIS(con, $$); : GETFIELD_INHERITANCE(con, $$); : : {
        CVMJITprintCodegenComment(("Do getfield:"));
        CVMJITaddCodegenComment((con, "value{D}"));
        fetchField(con, CVMRM_FP_REGS(con), $$,
		   GET_FLOAT_REGISTER_GOALS, CVMCPU_FLDR64_OPCODE, 2);
    };
%{
static void
moveIntToFPRegs(
    CVMJITCompilationContext* con,
    CVMJITIRNodePtr thisNode,
    CVMRMregset target,
    CVMRMregset avoid)
{
    CVMRMResource* src = popResource(con);
    CVMRMResource* dest;
    dest = CVMRMcloneResource(CVMRM_INT_REGS(con), src,
			      CVMRM_FP_REGS(con), target, avoid);
    CVMRMrelinquishResource(CVMRM_INT_REGS(con), src);
    /*
     * unpin without occupying
     * to occupy would cause big trouble if the thing is an
     * IDENT.
     */
    CVMRMunpinResource(CVMRM_FP_REGS(con), dest);
    pushResource(con, dest);
}

static void
moveFPToIntRegs(
    CVMJITCompilationContext* con,
    CVMJITIRNodePtr thisNode,
    CVMRMregset target,
    CVMRMregset avoid)
{
    CVMRMResource* src = popResource(con);
    CVMRMResource* dest;
    /* will cloneResource pin or not? Yes */
    dest = CVMRMcloneResource(CVMRM_FP_REGS(con), src, CVMRM_INT_REGS(con),
			      target, avoid);
    CVMRMrelinquishResource(CVMRM_FP_REGS(con), src);
    /*
     * unpin without occupying
     * to occupy would cause big trouble if the thing is an
     * FIDENT.
     */
    CVMRMunpinResource(CVMRM_INT_REGS(con), dest);
    pushResource(con, dest);
}

static CVMBool
canDoFloatLoadstore(const ArrayElemInfo* ei, CVMBool isStore){
    int opcode =  (isStore) ? ei->floatStoreOpcode : ei->floatLoadOpcode;
    return (opcode != CVM_ILLEGAL_OPCODE);
}
%}

// Purpose: value32 = FETCH32(INDEX(arrayObject, arraySubscript))
freg32: FETCH32 INDEX regObj arraySubscript : 20 :
    ARRAY_LOAD_SYNTHESIS(con, $$); : ARRAY_LOAD_INHERITANCE(con, $$); : : {
	CVMJITIRNode* indexNode = CVMJITirnodeGetLeftSubtree($$);
	CVMUint16 typeId = CVMJITirnodeGetBinaryOp(indexNode)->data;
	const ArrayElemInfo* ei = &typeidToArrayElemInfo[typeId];
	if (canDoFloatLoadstore(ei, CVM_FALSE)){
	    indexedLoad(con, CVMRM_FP_REGS(con), $$, GET_FLOAT_REGISTER_GOALS);
	} else {
	    indexedLoad(con, CVMRM_INT_REGS(con), $$,
			CVMRM_ANY_SET, CVMRM_EMPTY_SET);
	    moveIntToFPRegs(con, $$, GET_FLOAT_REGISTER_GOALS);
	}

    };


// Purpose: value32 = FETCH32(INDEX(arrayObject, arraySubscript))
freg32: FETCH32 arrayIndex : 20 : :  : : {
	ScaledIndexInfo *sinfo = popScaledIndexInfo(con); /* peek */
	const ArrayElemInfo* ei = sinfo->elemInfo;
	pushScaledIndexInfo(con, sinfo);
        CVMJITprintCodegenComment(("Do *slotAddr32:"));
	if (canDoFloatLoadstore(ei, CVM_FALSE)){
	    fetchArraySlot(con, CVMRM_FP_REGS(con), $$,
			   GET_FLOAT_REGISTER_GOALS);
	}else{
	    fetchArraySlot(con, CVMRM_INT_REGS(con), $$,
			   CVMRM_ANY_SET, CVMRM_EMPTY_SET);
	    moveIntToFPRegs(con, $$, GET_FLOAT_REGISTER_GOALS);
	}

    };

// Purpose: value64 = FETCH64(INDEX(arrayObject, arraySubscript))
freg64: FETCH64 INDEX regObj arraySubscript : 20 :
    ARRAY_LOAD_SYNTHESIS(con, $$); : ARRAY_LOAD_INHERITANCE(con, $$); : : {
	CVMJITIRNode* indexNode = CVMJITirnodeGetLeftSubtree($$);
	CVMUint16 typeId = CVMJITirnodeGetBinaryOp(indexNode)->data;
	const ArrayElemInfo* ei = &typeidToArrayElemInfo[typeId];
	if (canDoFloatLoadstore(ei, CVM_FALSE)){
	    indexedLoad(con, CVMRM_FP_REGS(con), $$, GET_FLOAT_REGISTER_GOALS);
	} else {
	    indexedLoad(con, CVMRM_INT_REGS(con), $$,
			CVMRM_ANY_SET, CVMRM_EMPTY_SET);
	    moveIntToFPRegs(con, $$, GET_FLOAT_REGISTER_GOALS);
	}

    };


// Purpose: value64 = FETCH64(INDEX(arrayObject, arraySubscript))
freg64: FETCH64 arrayIndex : 20 : :  : : {
	ScaledIndexInfo *sinfo = popScaledIndexInfo(con); /* peek */
	const ArrayElemInfo* ei = sinfo->elemInfo;
	pushScaledIndexInfo(con, sinfo);
        CVMJITprintCodegenComment(("Do *slotAddr32:"));
	if (canDoFloatLoadstore(ei, CVM_FALSE)){
	    fetchArraySlot(con, CVMRM_FP_REGS(con), $$,
			   GET_FLOAT_REGISTER_GOALS);
	}else{
	    fetchArraySlot(con, CVMRM_INT_REGS(con), $$,
			   CVMRM_ANY_SET, CVMRM_EMPTY_SET);
	    moveIntToFPRegs(con, $$, GET_FLOAT_REGISTER_GOALS);
	}

    };

//
// pass floating registers as Java parameters.
// the odd cost is to force parameter passing without arithmetic
// to use integer registers.
//
//
param32: freg32 : 11 : : : : {
	CVMRMResource *operand = popResource(con);
	CVMSMpushSingle(con, CVMRM_FP_REGS(con), operand);
	CVMRMrelinquishResource(CVMRM_FP_REGS(con), operand);
    };
param64: freg64 : 22 : : : : {
	CVMRMResource *operand = popResource(con);
	CVMSMpushDouble(con, CVMRM_FP_REGS(con), operand);
	CVMRMrelinquishResource(CVMRM_FP_REGS(con), operand);
    };


//
// the odd cost on these is to force an assignment without
// arithmetic to use the integer registers. e.g.
//        ASSIGN
//         /   \
//    LOCAL32 LOCAL32
//
root:	ASSIGN LOCAL32 freg32 : 11 : : : : {
	CVMRMResource* rhs = popResource(con);
	CVMJITLocal*   lhs = CVMJITirnodeGetLocal(
		CVMJITirnodeGetLeftSubtree($$));
	CVMRMpinResource(CVMRM_FP_REGS(con), rhs,
			 CVMRM_FP_ANY_SET, CVMRM_EMPTY_SET);
	CVMRMstoreJavaLocal(CVMRM_FP_REGS(con), rhs, 1, CVM_FALSE, lhs->localNo);
	CVMRMrelinquishResource(CVMRM_FP_REGS(con), rhs);
    };

// Purpose: ASSIGN(FIELDREF32(obj,fieldOffset), value32)
root: ASSIGN FIELDREF32 regObj memSpec freg32 : 11 :
    PUTFIELD_SYNTHESIS(con, $$); : PUTFIELD_INHERITANCE(con, $$); : : {
        CVMJITprintCodegenComment(("Do putfield:"));
        CVMJITaddCodegenComment((con,
            "putfield(obj, fieldOffset, value{I|F});"));
        setField(con, CVMRM_FP_REGS(con), CVMCPU_FSTR32_OPCODE);
    };

// Purpose: STATIC32(staticFieldSpec) = value32.
root: ASSIGN STATIC32 memSpec freg32 : 21 : : : : {
        CVMJITprintCodegenComment(("Do putstatic:"));
        CVMJITaddCodegenComment((con,
            "putstatic(staticFieldAddr, value{I|F|O})"));
        setStaticField(con, CVMRM_FP_REGS(con), CVMCPU_FSTR32_OPCODE);
    };

root:	IRETURN freg32: 11 : : : : {
        /* Emit the one-way ticket home: */
        emitReturn(con, CVMRM_FP_REGS(con), 1);
    };

// Purpose: ASSIGN(INDEX(arrayObject, arraySubscript), value32)
root: ASSIGN INDEX regObj arraySubscript freg32 : 21 :
    ARRAY_STORE_SYNTHESIS(con, $$); : ARRAY_STORE_INHERITANCE(con, $$); : : {
	CVMJITIRNode* indexNode = CVMJITirnodeGetLeftSubtree($$);
	CVMUint16 typeId = CVMJITirnodeGetBinaryOp(indexNode)->data;
	const ArrayElemInfo* ei = &typeidToArrayElemInfo[typeId];
	if (canDoFloatLoadstore(ei, CVM_TRUE)){
	    indexedStore(con, CVMRM_FP_REGS(con), $$);
	} else {
	    moveFPToIntRegs(con, NULL, CVMRM_ANY_SET, CVMRM_EMPTY_SET);
	    indexedStore(con, CVMRM_INT_REGS(con), $$);
	}
    };

// Purpose: ASSIGN(INDEX(arrayObject, arraySubscript), value32)
root: ASSIGN arrayIndex freg32 : 21 : : : : {
	CVMRMResource* rhs = popResource(con);
	ScaledIndexInfo *sinfo = popScaledIndexInfo(con); /* peek */
	const ArrayElemInfo* ei = sinfo->elemInfo;
	pushScaledIndexInfo(con, sinfo);
	pushResource(con, rhs);
        CVMJITprintCodegenComment(("*slotAddr32 = freg:"));
	if (canDoFloatLoadstore(ei, CVM_TRUE)){
	    storeArraySlot(con, CVMRM_FP_REGS(con), $$);