jitciscemitter_cpu.h

来自「This is a resource based on j2me embedde」· C头文件 代码 · 共 583 行 · 第 1/2 页

/*
 * @(#)jitciscemitter_cpu.h	1.5 06/10/24
 * 
 * Portions Copyright  2000-2008 Sun Microsystems, Inc. All Rights
 * Reserved.  Use is subject to license terms.
 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER
 * 
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version
 * 2 only, as published by the Free Software Foundation.
 * 
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
 * General Public License version 2 for more details (a copy is
 * included at /legal/license.txt).
 * 
 * You should have received a copy of the GNU General Public License
 * version 2 along with this work; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 * 
 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
 * Clara, CA 95054 or visit www.sun.com if you need additional
 * information or have any questions.
 */

#ifndef _INCLUDED_X86_JITCISCEMITTER_CPU_H
#define _INCLUDED_X86_JITCISCEMITTER_CPU_H

/*
 * This file #defines all of the emitter function prototypes and
 * macros that shared parts use in a platform indendent way in CISC
 * ports of the jit back end.
 *
 * The exported functions and macros are prefixed with CVMCPU_.  
 * 
 * Other functions and macros should be considered private to the X86
 * specific parts of the jit, including those with the CVMX86_ prefix.
 */

/**********************************************************************
 * Our stack layout and the names of the registers we're going to use
 * to access it:
 *
 *	+----------------------
 *	| Java local 0
 *	+----------------------
 *	...
 *	+----------------------
 *	| Java local n
 *	+----------------------
 * JFP->| control information here
 *	| of some size...
 *	+----------------------
 *	| Java temp 0	( code generation allocated )
 *	+----------------------
 *	...
 *	+----------------------
 *	| Java temp n	( code generation allocated )
 *	+----------------------
 * JSP->| Outgoing Java parameters.
 *	+----------------------
 *
 * Java locals and temps accessed via JFP,
 * JSP  used to access only the stack top.
 *
 * In truth, we really only need JSP, since the offsets of everything
 * else are known at compilation of each instruction. But we could never
 * debug the resulting code! This seems like a bad idea in the short run.
 *
 * DK: Seems that all this can be reused for the CISC interface.
 */

/**************************************************************
 * CPU ALURhs and associated types - The following are function
 * prototypes and macros for the ALURhs abstraction required by
 * the CISC emitter porting layer.
 **************************************************************/

/* ALURhs constructors and query APIs: ==================================== */

#define CVMX86_MAX_RHS_IMMEDIATE_OFFSET 0x7fffffff /* == max_int <= - min_int */


#define CVMCPUalurhsIsEncodableAsImmediate(constValue) \
    ((CVMInt32)(constValue) <= CVMX86_MAX_RHS_IMMEDIATE_OFFSET && \
     (CVMInt32)(constValue) >= (-CVMX86_MAX_RHS_IMMEDIATE_OFFSET - 1))

#define CVMCPUalurhsIsConstant(aluRhs) \
    ((aluRhs)->type == CVMCPU_ALURHS_CONSTANT)

#define CVMCPUalurhsGetConstantValue(aluRhs)    ((aluRhs)->constValue)

/* ALURhs token encoder APIs:============================================= */

/* Purpose: Gets the token for the ALURhs value for use in the instruction
            emitters. */
CVMCPUALURhsToken
CVMX86alurhsGetToken(CVMJITCompilationContext* con, const CVMCPUALURhs *aluRhs);

#define CVMCPUalurhsGetToken(con, aluRhs)  CVMX86alurhsGetToken((con), (aluRhs))

/* Purpose: Encodes an CVMCPUALURhsToken for the specified arguments. */
/* NOTE: This function is private to the X86 implementation and can only be
         called from the shared implementation via the CVMCPUxxx macros
         below. */
CVMCPUALURhsToken
CVMX86alurhsEncodeToken(CVMJITCompilationContext *con, CVMCPUALURhsType type, 
			int constValue, int rRegID);

/* Purpose: Encodes a CVMCPUALURhsToken for the specified constant value. */
#define CVMCPUalurhsEncodeConstantToken(con, constValue) \
     CVMX86alurhsEncodeToken((con), CVMCPU_ALURHS_CONSTANT, (constValue), \
         CVMCPU_INVALID_REG)

#define CVMCPUalurhsEncodeRegisterToken(con, regID) \
     CVMX86alurhsEncodeToken((con), CVMCPU_ALURHS_REGISTER, -1, (regID))

/**************************************************************
 * CPU MemSpec and associated types - The following are function
 * prototypes and macros for the MemSpec abstraction required by
 * the CISC emitter porting layer.
 **************************************************************/

/* MemSpec query APIs: ==================================================== */

#define CVMCPUmemspecIsEncodableAsImmediate(value) \
    ((INT_MIN <= ((CVMInt32)(value))) && (((CVMInt32)(value)) <= INT_MAX))

#define CVMCPUmemspecIsEncodableAsOpcodeSpecificImmediate(opcode, value) \
    CVMCPUmemspecIsEncodableAsImmediate(value)

/* MemSpec token encoder APIs: ============================================ */

/* Purpose: Encodes a CVMCPUMemSpecToken from the specified memSpec. */
CVMCPUMemSpecToken
CVMX86memspecGetToken(CVMJITCompilationContext *con, const CVMCPUMemSpec *memSpec);

#define CVMCPUmemspecGetToken(con, memSpec) \
    ((void)(con), CVMX86memspecGetToken((con), memSpec))

/* Allocates a new token and returns it. All memoryspec types are supported,
   except for auto-modify addressing modes. */
CVMCPUMemSpecToken
CVMX86memspecEncodeToken(CVMJITCompilationContext *con,
			 CVMCPUMemSpecType type, int offset, int regid, int scale);

#define CVMCPUmemspecEncodeImmediateToken(con, offset) \
    ((void)(con), CVMX86memspecEncodeToken((con), CVMCPU_MEMSPEC_IMMEDIATE_OFFSET, \
                      (offset), (offset), CVMX86times_1))

#define CVMCPUmemspecEncodeAbsoluteToken(con, address)				\
    ((void)(con), CVMX86memspecEncodeToken((con), CVMCPU_MEMSPEC_ABSOLUTE,	\
                      (address), (address), CVMX86times_1))

/* NOTE: X86 does not support post-increment and pre-decrement memory
   access. Extra add/sub instruction is emitted in order to achieve
   it. */
#define CVMCPUmemspecEncodePreDecrementImmediateToken(con, decrement)         \
    ((void)(con), CVMassert(CVMCPUmemspecIsEncodableAsImmediate(decrement)),  \
     CVMX86memspecEncodeToken((con), CVMCPU_MEMSPEC_PREDECREMENT_IMMEDIATE_OFFSET, \
                                (decrement), (decrement), CVMX86times_1))

/**************************************************************
 * CPU code emitters - The following are prototypes of code
 * emitters required by the CISC emitter porting layer.
 **************************************************************/

/* ===== 32 Bit ALU Emitter APIs ========================================== */

#define CVMCPUemitBinaryALURegister(con, opcode, destRegID, lhsRegID, \
                                    rhsRegID, setcc) \
    CVMCPUemitBinaryALU((con), (opcode), (destRegID), (lhsRegID), \
        CVMCPUalurhsEncodeRegisterToken((con), (rhsRegID)), (setcc))

#define CVMCPUemitMoveRegister(con, opcode, destRegID, srcRegID, setcc) \
    CVMCPUemitMove((con), (opcode), (destRegID), \
        CVMCPUalurhsEncodeRegisterToken((con), (srcRegID)), (setcc))

/* ===== Branch Emitter APIs ========================================== */
#define CVMCPUemitBranch(con, target, condCode) \
    CVMCPUemitBranchNeedFixup((con), (target), (condCode), NULL)

#define CVMCPUemitBranchLink(con, target) \
    CVMCPUemitBranchLinkNeedFixup((con), (target), NULL)

/*
 * Make a PC-relative branch or branch-and-link instruction
 */
CVMCPUInstruction
CVMX86getBranchInstruction(int opcode, CVMCPUCondCode condCode, int offset);

/*
 * Make a PC-relative branch or branch-and-link instruction.
 */
void
CVMX86emitBranch(CVMJITCompilationContext* con,
                 int logicalPC, CVMCPUCondCode condCode /*, CVMBool annul */);


/**************************************************************
 * x86 Assembler
 **************************************************************/

void CVMX86emit_byte(CVMJITCompilationContext* con, int x);
void CVMX86emit_word(CVMJITCompilationContext* con, int x);
void CVMX86emit_long(CVMJITCompilationContext* con, CVMInt32 x);

/* accessors */
CVMBool CVMCPUAddress_uses(CVMCPUAddress addr, CVMCPURegister reg);

/* creation */
CVMCPUAddress* 
CVMCPUinit_Address(CVMCPUAddress *addr, CVMCPUMemSpecType type);

CVMCPUAddress* 
CVMCPUinit_Address_disp(CVMCPUAddress *addr, int disp, CVMCPUMemSpecType type);

CVMCPUAddress* 
CVMCPUinit_Address_base_disp(CVMCPUAddress *addr, CVMCPURegister base, 
			     int disp, CVMCPUMemSpecType type);

CVMCPUAddress* 
CVMCPUinit_Address_base_memspec(CVMCPUAddress *addr, CVMCPURegister base, 
				CVMCPUMemSpec *ms);

CVMCPUAddress* 
CVMCPUinit_Address_base_memspectoken(CVMCPUAddress *addr, CVMCPURegister base, 
				     CVMCPUMemSpecToken mst);

CVMCPUAddress* 
CVMCPUinit_Address_base_idx_scale_disp(CVMCPUAddress* addr, CVMCPURegister base,
				       CVMCPURegister index, CVMCPUScaleFactor scale, 
				       int disp, CVMCPUMemSpecType type);

void CVMX86emit_data(CVMJITCompilationContext* con, CVMInt32 data);

/* Helper functions for groups of instructions */
void CVMX86emit_arith_reg_imm8(CVMJITCompilationContext* con, int op1, int op2, CVMX86Register dst, int imm8);
void CVMX86emit_arith_reg_reg(CVMJITCompilationContext* con, int op1, int op2, CVMX86Register dst, CVMX86Register src);
void CVMX86emit_farith(CVMJITCompilationContext* con, int b1, int b2, int i);


/* Stack */
void CVMX86pushad(CVMJITCompilationContext* con);
void CVMX86popad(CVMJITCompilationContext* con);

void CVMX86pushfd(CVMJITCompilationContext* con);
void CVMX86popfd(CVMJITCompilationContext* con);

void CVMX86pushl_imm32(CVMJITCompilationContext* con, int imm32);
void CVMX86pushl_reg(CVMJITCompilationContext* con, CVMX86Register src);
void CVMX86pushl_mem(CVMJITCompilationContext* con, CVMX86Address src);

void CVMX86popl_reg(CVMJITCompilationContext* con, CVMX86Register dst);
void CVMX86popl_mem(CVMJITCompilationContext* con, CVMX86Address dst);

/* Instruction prefixes */
void CVMX86prefix(CVMJITCompilationContext* con, CVMX86Prefix p);

/* Moves */
void CVMX86movb_reg_mem(CVMJITCompilationContext* con, CVMX86Register dst, CVMX86Address src);
void CVMX86movb_reg_imm8(CVMJITCompilationContext* con, CVMX86Address dst, int imm8);
void CVMX86movb_reg_reg(CVMJITCompilationContext* con, CVMX86Address dst, CVMX86Register src);

void CVMX86movw_reg_imm16(CVMJITCompilationContext* con, CVMX86Address dst, int imm16);
void CVMX86movw_reg_mem(CVMJITCompilationContext* con, CVMX86Register dst, CVMX86Address src);
void CVMX86movw_mem_reg(CVMJITCompilationContext* con, CVMX86Address dst, CVMX86Register src);


/*
   ================ movl   reg, operand =================
*/
void CVMX86movl_reg_imm32(CVMJITCompilationContext* con, CVMX86Register dst, 
			  int imm32);
void CVMX86movl_reg_reg(CVMJITCompilationContext* con, CVMX86Register dst, CVMX86Register src);
void CVMX86movl_reg_mem(CVMJITCompilationContext* con, CVMX86Register dst, CVMX86Address src);


/*
   ================ movl   mem, operand =================
*/
void CVMX86movl_mem_imm32(CVMJITCompilationContext* con, CVMX86Address dst, 
			  int imm32);

void CVMX86movl_mem_reg(CVMJITCompilationContext* con, CVMX86Address dst, CVMX86Register src);


void CVMX86movsxb_reg_mem(CVMJITCompilationContext* con, CVMX86Register dst, CVMX86Address src);
void CVMX86movsxb_reg_reg(CVMJITCompilationContext* con, CVMX86Register dst, CVMX86Register src);