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📄 hahahacheng.mdl

📁 自己毕业设计一些收集和做的一些simulink模型及源码
💻 MDL
📖 第 1 页 / 共 5 页
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	  Inputs		  "2"
	  DisplayOption		  "bar"
	}
	Block {
	  BlockType		  Outport
	  Name			  "ualfa"
	  Position		  [325, 53, 355, 67]
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "ubeta"
	  Position		  [325, 173, 355, 187]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "ua"
	  SrcPort		  1
	  Points		  [35, 0; 0, 15]
	  DstBlock		  "Mux"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "ub"
	  SrcPort		  1
	  Points		  [30, 0]
	  Branch {
	    Points		    [15, 0; 0, -30]
	    DstBlock		    "Mux"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, 80]
	    DstBlock		    "Mux1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "uc"
	  SrcPort		  1
	  Points		  [10, 0]
	  Branch {
	    Points		    [60, 0]
	    DstBlock		    "Mux"
	    DstPort		    3
	  }
	  Branch {
	    Points		    [0, 50]
	    DstBlock		    "Mux1"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Mux"
	  SrcPort		  1
	  DstBlock		  "Fcn"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Fcn"
	  SrcPort		  1
	  DstBlock		  "ualfa"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Mux1"
	  SrcPort		  1
	  DstBlock		  "Fcn1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Fcn1"
	  SrcPort		  1
	  DstBlock		  "ubeta"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Subsystem4"
      Ports		      [4, 1]
      Position		      [1140, 59, 1200, 316]
      ShowName		      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      MaskHideContents	      off
      System {
	Name			"Subsystem4"
	Location		[92, 129, 517, 365]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "PHIalfa"
	  Position		  [25, 148, 55, 162]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "PHIbeta"
	  Position		  [30, 198, 60, 212]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "ialfa"
	  Position		  [25, 28, 55, 42]
	  Port			  "3"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "ibeta"
	  Position		  [25, 88, 55, 102]
	  Port			  "4"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Sum
	  Name			  "Add4"
	  Ports			  [2, 1]
	  Position		  [235, 82, 265, 113]
	  ShowName		  off
	  Inputs		  "-+"
	  CollapseMode		  "All dimensions"
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  OutScaling		  "2^-10"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Gain
	  Name			  "Gain"
	  Position		  [300, 85, 330, 115]
	  Gain			  "3"
	  ParameterDataTypeMode	  "Inherit via internal rule"
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Product
	  Name			  "Product"
	  Ports			  [2, 1]
	  Position		  [150, 92, 180, 123]
	  NamePlacement		  "alternate"
	  ShowName		  off
	  CollapseMode		  "All dimensions"
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Product
	  Name			  "Product1"
	  Ports			  [2, 1]
	  Position		  [150, 47, 180, 78]
	  NamePlacement		  "alternate"
	  ShowName		  off
	  CollapseMode		  "All dimensions"
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Te"
	  Position		  [370, 93, 400, 107]
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "ialfa"
	  SrcPort		  1
	  Points		  [0, 20]
	  DstBlock		  "Product1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "PHIbeta"
	  SrcPort		  1
	  Points		  [0, -135]
	  DstBlock		  "Product1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Product1"
	  SrcPort		  1
	  Points		  [15, 0; 0, 25]
	  DstBlock		  "Add4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "ibeta"
	  SrcPort		  1
	  Points		  [75, 0]
	  DstBlock		  "Product"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "PHIalfa"
	  SrcPort		  1
	  Points		  [75, 0]
	  DstBlock		  "Product"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Product"
	  SrcPort		  1
	  Points		  [15, 0; 0, -5]
	  DstBlock		  "Add4"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Add4"
	  SrcPort		  1
	  DstBlock		  "Gain"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Gain"
	  SrcPort		  1
	  DstBlock		  "Te"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Subsystem5"
      Ports		      [4, 2]
      Position		      [985, 55, 1045, 185]
      ShowName		      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      MaskHideContents	      off
      System {
	Name			"Subsystem5"
	Location		[129, 164, 594, 383]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "ualfa"
	  Position		  [25, 23, 55, 37]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "ubeta"
	  Position		  [25, 123, 55, 137]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "ialfa"
	  Position		  [25, 68, 55, 82]
	  Port			  "3"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "ibeta"
	  Position		  [30, 168, 60, 182]
	  Port			  "4"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Sum
	  Name			  "Add"
	  Ports			  [2, 1]
	  Position		  [265, 132, 295, 163]
	  ShowName		  off
	  Inputs		  "+-"
	  CollapseMode		  "All dimensions"
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  OutScaling		  "2^-10"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Sum
	  Name			  "Add1"
	  Ports			  [2, 1]
	  Position		  [265, 72, 295, 103]
	  ShowName		  off
	  Inputs		  "+-"
	  CollapseMode		  "All dimensions"
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  OutScaling		  "2^-10"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Integrator
	  Name			  "Integrator"
	  Ports			  [1, 1]
	  Position		  [315, 135, 345, 165]
	  ShowName		  off
	  IgnoreLimit		  off
	}
	Block {
	  BlockType		  Integrator
	  Name			  "Integrator1"
	  Ports			  [1, 1]
	  Position		  [315, 75, 345, 105]
	  ShowName		  off
	  IgnoreLimit		  off
	}
	Block {
	  BlockType		  Gain
	  Name			  "Rs"
	  Position		  [195, 80, 225, 110]
	  ShowName		  off
	  Gain			  "2.875"
	  ParameterDataTypeMode	  "Inherit via internal rule"
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Gain
	  Name			  "Rs1"
	  Position		  [155, 160, 185, 190]
	  ShowName		  off
	  Gain			  "2.875"
	  ParameterDataTypeMode	  "Inherit via internal rule"
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Outport
	  Name			  "PHIalfa"
	  Position		  [410, 83, 440, 97]
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "PHIbeta"
	  Position		  [410, 143, 440, 157]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "Add"
	  SrcPort		  1
	  DstBlock		  "Integrator"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Add1"
	  SrcPort		  1
	  DstBlock		  "Integrator1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "ialfa"
	  SrcPort		  1
	  Points		  [120, 0]
	  DstBlock		  "Rs"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Rs"
	  SrcPort		  1
	  DstBlock		  "Add1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "ualfa"
	  SrcPort		  1
	  Points		  [185, 0; 0, 50]
	  DstBlock		  "Add1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Rs1"
	  SrcPort		  1
	  Points		  [60, 0]
	  DstBlock		  "Add"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "ibeta"
	  SrcPort		  1
	  DstBlock		  "Rs1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "ubeta"
	  SrcPort		  1
	  Points		  [50, 0; 0, 5; 140, 0]
	  DstBlock		  "Add"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Integrator1"
	  SrcPort		  1
	  DstBlock		  "PHIalfa"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Integrator"
	  SrcPort		  1
	  DstBlock		  "PHIbeta"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Subsystem6"
      Ports		      [2, 2]
      Position		      [885, 430, 945, 505]
      Orientation	      "left"
      ShowName		      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      MaskHideContents	      off
      System {
	Name			"Subsystem6"
	Location		[42, 110, 572, 263]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "PHIalfa"
	  Position		  [25, 28, 55, 42]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "PHIbeta"
	  Position		  [15, 83, 45, 97]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  ComplexToMagnitudeAngle
	  Name			  "Complex to\nMagnitude-Angle"
	  Ports			  [1, 2]
	  Position		  [165, 38, 195, 67]
	  NamePlacement		  "alternate"
	  ShowName		  off
	  Output		  "Magnitude and angle"
	}
	Block {
	  BlockType		  Gain
	  Name			  "Rad2Deg"
	  Position		  [275, 90, 305, 120]
	  NamePlacement		  "alternate"
	  Gain			  "180/pi"
	}
	Block {
	  BlockType		  RealImagToComplex
	  Name			  "Real-Imag to\nComplex"
	  Ports			  [2, 1]
	  Position		  [95, 38, 125, 67]
	  ShowName		  off
	}
	Block {
	  BlockType		  ZeroOrderHold
	  Name			  "Zero-Order\nHold1"
	  Position		  [325, 95, 345, 115]
	  NamePlacement		  "alternate"
	  ShowName		  off
	  FontSize		  12
	  SampleTime		  "2.0000e-005"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "a_b_vector_sector"
	  Ports			  [1, 1]
	  Position		  [365, 79, 445, 131]
	  NamePlacement		  "alternate"
	  ShowName		  off
	  MinAlgLoopOccurrences	  off
	  RTWSystemCode		  "Au

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