📄 chenggong.mdl
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VectorParams1D on
SamplingMode "Sample based"
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
SampleTime "inf"
FramePeriod "inf"
}
Block {
BlockType DataTypeConversion
OutDataTypeMode "Inherit via back propagation"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
ConvertRealWorld "Real World Value (RWV)"
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Demux
Outputs "4"
DisplayOption "none"
BusSelectionMode off
}
Block {
BlockType Derivative
LinearizePole "inf"
}
Block {
BlockType ElementaryMath
Operator "sin"
}
Block {
BlockType EnablePort
StatesWhenEnabling "held"
ShowOutputPort off
ZeroCross on
}
Block {
BlockType From
IconDisplay "Tag"
}
Block {
BlockType Fcn
Expr "sin(u[1])"
SampleTime "-1"
}
Block {
BlockType Gain
Gain "1"
Multiplication "Element-wise(K.*u)"
ParameterDataTypeMode "Same as input"
ParameterDataType "sfix(16)"
ParameterScalingMode "Best Precision: Matrix-wise"
ParameterScaling "2^0"
OutDataTypeMode "Same as input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Goto
IconDisplay "Tag"
}
Block {
BlockType Ground
}
Block {
BlockType Inport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchByCopyingInsideSignal off
Interpolate on
}
Block {
BlockType Integrator
ExternalReset "none"
InitialConditionSource "internal"
InitialCondition "0"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
IgnoreLimit off
ZeroCross on
ContinuousStateAttributes "''"
}
Block {
BlockType Logic
Operator "AND"
Inputs "2"
IconShape "rectangular"
AllPortsSameDT on
OutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
SampleTime "-1"
}
Block {
BlockType Lookup2D
RowIndex "[0 1]"
ColumnIndex "[0 1]"
OutputValues "[0 0;0 0]"
LookUpMeth "Interpolation-Extrapolation"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
LUTDesignTableMode "Redesign Table"
LUTDesignDataSource "Block Dialog"
LUTDesignFunctionName "sqrt(x)"
LUTDesignUseExistingBP on
LUTDesignRelError "0.01"
LUTDesignAbsError "1e-6"
}
Block {
BlockType Memory
X0 "0"
InheritSampleTime off
LinearizeMemory off
LinearizeAsDelay off
StateMustResolveToSignalObject off
RTWStateStorageClass "Auto"
}
Block {
BlockType MultiPortSwitch
Inputs "4"
zeroidx off
InputSameDT on
OutDataTypeMode "Inherit via internal rule"
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Mux
Inputs "4"
DisplayOption "none"
UseBusObject off
BusObject "BusObject"
NonVirtualBus off
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType PMComponent
SubClassName "unknown"
}
Block {
BlockType PMIOPort
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
CollapseMode "All dimensions"
CollapseDim "1"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType RealImagToComplex
Input "Real and imag"
ConstantPart "0"
SampleTime "-1"
}
Block {
BlockType Relay
OnSwitchValue "eps"
OffSwitchValue "eps"
OnOutputValue "1"
OffOutputValue "0"
OutputDataTypeScalingMode "All ports same datatype"
OutDataType "sfix(16)"
OutScaling "2^0"
ConRadixGroup "Use specified scaling"
ZeroCross on
SampleTime "-1"
}
Block {
BlockType RelationalOperator
Operator ">="
InputSameDT on
LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Saturate
UpperLimit "0.5"
LowerLimit "-0.5"
LinearizeAsGain on
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Selector
NumberOfDimensions "1"
IndexMode "One-based"
InputPortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Step
Time "1"
Before "0"
After "1"
SampleTime "-1"
VectorParams1D on
ZeroCross on
}
Block {
BlockType SubSystem
ShowPortLabels "FromPortIcon"
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
CollapseMode "All dimensions"
CollapseDim "1"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Switch
Criteria "u2 >= Threshold"
Threshold "0"
InputSameDT on
OutDataTypeMode "Inherit via internal rule"
RndMeth "Floor"
SaturateOnIntegerOverflow on
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Terminator
}
Block {
BlockType TransferFcn
Numerator "[1]"
Denominator "[1 2 1]"
AbsoluteTolerance "auto"
ContinuousStateAttributes "''"
Realization "auto"
}
Block {
BlockType Trigonometry
Operator "sin"
OutputSignalType "auto"
SampleTime "-1"
}
Block {
BlockType ZeroOrderHold
SampleTime "1"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
UseDisplayTextAsClickCallback off
}
LineDefaults {
FontName "Arial"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "chenggong"
Location [2, 80, 1262, 756]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Sum
Name "Add"
Ports [2, 1]
Position [935, 342, 965, 373]
Inputs "-+"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Sum
Name "Add1"
Ports [2, 1]
Position [910, 242, 940, 273]
Inputs "-+"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Sum
Name "Add2"
Ports [2, 1]
Position [220, 367, 250, 398]
Inputs "-+"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Sum
Name "Add3"
Ports [2, 1]
Position [85, 292, 115, 323]
ShowName off
Inputs "+-"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Sum
Name "Add4"
Ports [2, 1]
Position [1170, 420, 1200, 460]
Inputs "+-"
CollapseMode "All dimensions"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType BusSelector
Name "Bus\nSelector"
Ports [1, 6]
Position [700, 229, 720, 411]
ShowName off
OutputSignals "Stator current is_d (A),Stator current is_q (A)"
",Stator voltage Vs_d (V),Rotor angle thetam (rad),Stator voltage Vs_q (V),Rot"
"or speed wm (rad/s)"
Port {
PortNumber 1
Name "<Stator current is_d (A)>"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 2
Name "<Stator current is_q (A)>"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 3
Name "<Stator voltage Vs_d (V)>"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 4
Name "<Rotor angle thetam (rad)>"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 5
Name "<Stator voltage Vs_q (V)>"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
Port {
PortNumber 6
Name "<Rotor speed wm (rad/s)>"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType ComplexToMagnitudeAngle
Name "Complex to\nMagnitude-Angle"
Ports [1, 2]
Position [835, 573, 865, 602]
Orientation "left"
Output "Magnitude and angle"
}
Block {
BlockType Gain
Name "Gain"
Position [80, 200, 110, 230]
Gain "500"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain2"
Position [1205, 485, 1235, 515]
Orientation "down"
NamePlacement "alternate"
ShowName off
Gain "3"
}
Block {
BlockType Integrator
Name "Integrator"
Ports [1, 1]
Position [980, 345, 1010, 375]
IgnoreLimit off
}
Block {
BlockType Integrator
Name "Integrator1"
Ports [1, 1]
Position [960, 245, 990, 275]
IgnoreLimit off
}
Block {
BlockType Reference
Name "Measures"
Ports [0, 2, 0, 0, 0, 4, 3]
Position [475, 104, 555, 186]
NamePlacement "alternate"
FontSize 12
SourceBlock "electricdrivelib/AC drives/DTC Induction Motor "
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