reg52.h

attendace system on 8051 chipset from intel.

/************************************JBB************************************/

#ifndef _89C51RD2_H
#define _89C51RD2_H

/* 8052 Processor Declarations */

/*  BYTE Registers  */
sfr P0    = 0x80;
sfr P1    = 0x90;
sfr P2    = 0xA0;
sfr P3    = 0xB0; 
sfr PSW   = 0xD0;
sfr ACC   = 0xE0;
sfr B     = 0xF0;
sfr SP    = 0x81;
sfr DPL   = 0x82;
sfr DPH   = 0x83;
sfr PCON  = 0x87;
sfr TCON  = 0x88;
sfr TMOD  = 0x89;
sfr TL0   = 0x8A;
sfr TL1   = 0x8B;
sfr TH0   = 0x8C;
sfr TH1   = 0x8D;
sfr IE    = 0xA8;
sfr IP    = 0xB8;
sfr SCON  = 0x98;
sfr SBUF  = 0x99;

/*  8052 Extensions  */
sfr T2CON  = 0xC8;
sfr RCAP2L = 0xCA;
sfr RCAP2H = 0xCB;
sfr TL2    = 0xCC;
sfr TH2    = 0xCD;

/*  BIT Registers  */
/*  PSW  */
sbit CY    = 0xD7;
sbit AC    = 0xD6;
sbit F0    = 0xD5;
sbit RS1   = 0xD4;
sbit RS0   = 0xD3;
sbit OV    = 0xD2;
sbit P     = 0xD0;

/*  TCON  */
sbit TF1   = 0x8F;
sbit TR1   = 0x8E;
sbit TF0   = 0x8D;
sbit TR0   = 0x8C;
sbit IE1   = 0x8B;
sbit IT1   = 0x8A;
sbit IE0   = 0x89;
sbit IT0   = 0x88;

/*  IE  */
sbit EA    = 0xAF;
sbit ES    = 0xAC;
sbit ET1   = 0xAB;
sbit EX1   = 0xAA;
sbit ET0   = 0xA9;
sbit EX0   = 0xA8;

/*  IP  */
sbit PS    = 0xBC;
sbit PT1   = 0xBB;
sbit PX1   = 0xBA;
sbit PT0   = 0xB9;
sbit PX0   = 0xB8;

/*  P3  */
sbit RD    = 0xB7;
sbit WR    = 0xB6;
sbit T1    = 0xB5;
sbit T0    = 0xB4;
sbit INT1  = 0xB3;
sbit INT0  = 0xB2;
sbit TXD   = 0xB1;
sbit RXD   = 0xB0;

/*  SCON  */
sbit SM0   = 0x9F;
sbit SM1   = 0x9E;
sbit SM2   = 0x9D;
sbit REN   = 0x9C;
sbit TB8   = 0x9B;
sbit RB8   = 0x9A;
sbit TI    = 0x99;
sbit RI    = 0x98;

/*  8052 Extensions  */
/*  IE  */
sbit ET2   = 0xAD;

/*  IP  */
sbit PT2   = 0xBD;

/*  P1  */
sbit T2EX  = 0x91;
sbit T2    = 0x90;
        
/*  T2CON  */
sbit TF2    = 0xCF;
sbit EXF2   = 0xCE;
sbit RCLK   = 0xCD;
sbit TCLK   = 0xCC;
sbit EXEN2  = 0xCB;
sbit TR2    = 0xCA;
sbit C_T2   = 0xC9;
sbit CP_RL2 = 0xC8;

/* Watchdog timer registers */
sfr CMOD   =   0xD9;
sfr CCAPM4 =   0xDE;
sfr CCAP4H =   0xFE;
sfr CCAP4L =   0xEE;   
sfr CCON   =   0xD8;

#define ENABLE_WATCHDOG()       IE     = IE | 0x40;     \
                                CCON   = 0x40;          \
                                CCAPM4 = 0x4C;          \
                                CCAP4L = 0xFF;          \
                                CCAP4H = 0xFF;          \
                                CMOD   = 0xC1;          \
                                CCON   = 0x40;

#define DISABLE_WATCHDOG()      CMOD = 0x00;            \
                                CCON = 0x00;

sbit CE = 0x93;

sfr AUXR = 0x8E;

#define ENABLE_ONCHIP_XRAM()  AUXR = AUXR & 0xFD
#define ENABLE_OFFCHIP_XRAM() AUXR = AUXR | 0x02; CE = 0;

#define DISABLE_ONCHIP_XRAM()  ENABLE_OFFCHIP_XRAM()
#define DISABLE_OFFCHIP_XRAM() ENABLE_ONCHIP_XRAM()

#define BAUD_RATE_2400 0
#define BAUD_RATE_4800 1
#define BAUD_RATE_9600 2

#define ENABLE_INTERRUPTS()  EA = 1
#define DISABLE_INTERRUPTS() EA = 0

#define MAX_BANKS 2

sbit P2_5 = 0xA5;
sbit P2_6 = 0xA6;
sbit P2_7 = 0xA7;

/*char xdata first_cursor  = '