📄 aduc7026.equ
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@ @
@ Analog Devices Microconverter @
@ Equate file for GNU Arm AS @
@ ADuC7026.equ @
@ @
@ Rev 0.3 @
@ @
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@ MMR Base Locations
.equ MMR_BASE_LOW, 0XFFFF0000
.equ MMR_BASE_HIGH, 0XFFFFF000
@ INTERRUPT CONTROLLER
.equ IRQBASE, 0XFFFF0000
.equ IRQSTA, 0XFFFF0000
.equ IRQSIG, 0XFFFF0004
.equ IRQEN, 0XFFFF0008
.equ IRQCLR, 0XFFFF000C
.equ SWICFG, 0XFFFF0010
.equ FIQSTA, 0XFFFF0100
.equ FIQSIG, 0XFFFF0104
.equ FIQEN, 0XFFFF0108
.equ FIQCLR, 0XFFFF010C
.equ IRQSTA_OFFSET, 0X0000
.equ IRQSIG_OFFSET, 0X0004
.equ IRQEN_OFFSET, 0X0008
.equ IRQCLR_OFFSET, 0X000C
.equ SWICFG_OFFSET, 0X0010
.equ FIQSTA_OFFSET, 0X0100
.equ FIQSIG_OFFSET, 0X0104
.equ FIQEN_OFFSET, 0X0108
.equ FIQCLR_OFFSET, 0X010C
@ REMAP AND SYSTEM CONTROL
.equ REMAPBASE, 0XFFFF0200
.equ REMAP, 0XFFFF0220
.equ RSTSTA, 0XFFFF0230
.equ RSTCLR, 0XFFFF0234
.equ REMAP_OFFSET, 0X0220
.equ RSTSTA_OFFSET, 0X0230
.equ RSTCLR_OFFSET, 0X0234
@ TIMER 0
.equ T0BASE, 0XFFFF0300
.equ T0LD, 0XFFFF0300
.equ T0VAL, 0XFFFF0304
.equ T0CON, 0XFFFF0308
.equ T0CLRI, 0XFFFF030C
.equ T0LD_OFFSET, 0X0300
.equ T0VAL_OFFSET, 0X0304
.equ T0CON_OFFSET, 0X0308
.equ T0CLRI_OFFSET, 0X030C
@ GENERAL PURPOSE TIMER
.equ T1BASE, 0XFFFF0320
.equ T1LD, 0XFFFF0320
.equ T1VAL, 0XFFFF0324
.equ T1CON, 0XFFFF0328
.equ T1CLRI, 0XFFFF032C
.equ T1CAP, 0XFFFF0330
.equ T1LD_OFFSET, 0X0320
.equ T1VAL_OFFSET, 0X0324
.equ T1CON_OFFSET, 0X0328
.equ T1CLRI_OFFSET, 0X032C
.equ T1CAP_OFFSET, 0X0330
@ WAKE UP TIMER
.equ T2BASE, 0XFFFF0340
.equ T2LD, 0XFFFF0340
.equ T2VAL, 0XFFFF0344
.equ T2CON, 0XFFFF0348
.equ T2CLRI, 0XFFFF034C
.equ T2LD_OFFSET, 0X0340
.equ T2VAL_OFFSET, 0X0344
.equ T2CON_OFFSET, 0X0348
.equ T2CLRI_OFFSET, 0X034C
@ WATCHDOG TIMER
.equ T3BASE, 0XFFFF0360
.equ T3LD, 0XFFFF0360
.equ T3VAL, 0XFFFF0364
.equ T3CON, 0XFFFF0368
.equ T3CLRI, 0XFFFF036C
.equ T3LD_OFFSET, 0X0360
.equ T3VAL_OFFSET, 0X0364
.equ T3CON_OFFSET, 0X0368
.equ T3CLRI_OFFSET, 0X036C
@ PLL AND OSCILLATOR CONTROL
.equ PLLBASE, 0XFFFF0400
.equ POWKEY1, 0XFFFF0404
.equ POWCON, 0XFFFF0408
.equ POWKEY2, 0XFFFF040C
.equ PLLKEY1, 0XFFFF0410
.equ PLLCON, 0XFFFF0414
.equ PLLKEY2, 0XFFFF0418
.equ POWKEY1_OFFSET, 0X0404
.equ POWCON_OFFSET, 0X0408
.equ POWKEY2_OFFSET, 0X040C
.equ PLLKEY1_OFFSET, 0X0410
.equ PLLCON_OFFSET, 0X0414
.equ PLLKEY2_OFFSET, 0X0418
@ POWER SUPPLY MONITOR
.equ PSMBASE, 0XFFFF0440
.equ PSMCON, 0XFFFF0440
.equ CMPCON, 0XFFFF0444
.equ PSMCON_OFFSET, 0X0440
.equ CMPCON_OFFSET, 0X0444
@ Band Gap Reference
.equ REFBASE, 0xffff0480
.equ REFCON, 0xffff048C
.equ REFCON_OFFSET, 0X048C
@ ADC INTERFACE REGISTERS
.equ ADCBASE, 0XFFFF0500
.equ ADCCON, 0XFFFF0500
.equ ADCCP, 0XFFFF0504
.equ ADCCN, 0XFFFF0508
.equ ADCSTA, 0XFFFF050C
.equ ADCDAT, 0XFFFF0510
.equ ADCRST, 0XFFFF0514
.equ ADCGN, 0XFFFF0530
.equ ADCOF, 0XFFFF0534
.equ ADCCON_OFFSET, 0X0500
.equ ADCCP_OFFSET, 0X0504
.equ ADCCN_OFFSET, 0X0508
.equ ADCSTA_OFFSET, 0X050C
.equ ADCDAT_OFFSET, 0X0510
.equ ADCRST_OFFSET, 0X0514
.equ ADCGN_OFFSET, 0X0530
.equ ADCOF_OFFSET, 0X0534
@ DAC INTERFACE REGISTERS
.equ DACBASE, 0XFFFF0600
.equ DAC0CON, 0XFFFF0600
.equ DAC0DAT, 0XFFFF0604
.equ DAC1CON, 0XFFFF0608
.equ DAC1DAT, 0XFFFF060C
.equ DAC2CON, 0XFFFF0610
.equ DAC2DAT, 0XFFFF0614
.equ DAC3CON, 0XFFFF0618
.equ DAC3DAT, 0XFFFF061C
.equ DAC0CON_OFFSET, 0X0600
.equ DAC0DAT_OFFSET, 0X0604
.equ DAC1CON_OFFSET, 0X0608
.equ DAC1DAT_OFFSET, 0X060C
.equ DAC2CON_OFFSET, 0X0610
.equ DAC2DAT_OFFSET, 0X0614
.equ DAC3CON_OFFSET, 0X0618
.equ DAC3DAT_OFFSET, 0X061C
@ EXTERNAL MEMORY REGISTERS
.equ XMBASE, 0XFFFFF000
.equ XMCFG, 0XFFFFF000
.equ XM0CON, 0XFFFFF010
.equ XM1CON, 0XFFFFF014
.equ XM2CON, 0XFFFFF018
.equ XM3CON, 0XFFFFF01C
.equ XM0PAR, 0XFFFFF020
.equ XM1PAR, 0XFFFFF024
.equ XM2PAR, 0XFFFFF028
.equ XM3PAR, 0XFFFFF02C
@ 450 COMPATIABLE UART CORE REGISTERS
.equ UARTBASE, 0XFFFF0700
.equ COMTX, 0XFFFF0700
.equ COMRX, 0XFFFF0700
.equ COMDIV0, 0XFFFF0700
.equ COMIEN0, 0XFFFF0704
.equ COMDIV1, 0XFFFF0704
.equ COMIID0, 0XFFFF0708
.equ COMCON0, 0XFFFF070C
.equ COMCON1, 0XFFFF0710
.equ COMSTA0, 0XFFFF0714
.equ COMSTA1, 0XFFFF0718
.equ COMSCR, 0XFFFF071C
.equ COMVAL, 0XFFFF071C
.equ COMIEN1, 0XFFFF0720
.equ COMIID1, 0XFFFF0724
.equ COMADR, 0XFFFF0728
.equ COMDIV2, 0XFFFF072C
.equ COMTX_OFFSET, 0X0700
.equ COMRX_OFFSET, 0X0700
.equ COMDIV0_OFFSET, 0X0700
.equ COMIEN0_OFFSET, 0X0704
.equ COMDIV1_OFFSET, 0X0704
.equ COMIID0_OFFSET, 0X0708
.equ COMCON0_OFFSET, 0X070C
.equ COMCON1_OFFSET, 0X0710
.equ COMSTA0_OFFSET, 0X0714
.equ COMSTA1_OFFSET, 0X0718
.equ COMSCR_OFFSET, 0X071C
.equ COMVAL_OFFSET, 0X071C
.equ COMIEN1_OFFSET, 0X0720
.equ COMIID1_OFFSET, 0X0724
.equ COMADR_OFFSET, 0X0728
.equ COMDIV2_OFFSET, 0X072C
@ I2C BUS PERIPHERAL DEVICE
.equ I2CBASE, 0XFFFF0800
.equ I2CMSTA, 0XFFFF0800
.equ I2CSSTA, 0XFFFF0804
.equ I2CSRX, 0XFFFF0808
.equ I2CSTX, 0XFFFF080C
.equ I2CMRX, 0XFFFF0810
.equ I2CMTX, 0XFFFF0814
.equ I2CCNT, 0XFFFF0818
.equ I2CADR, 0XFFFF081C
.equ I2CBYTE, 0XFFFF0824
.equ I2CALT, 0XFFFF0828
.equ I2CCFG, 0XFFFF082C
.equ I2CDIV, 0XFFFF0830
.equ I2CID0, 0XFFFF0838
.equ I2CID1, 0XFFFF083C
.equ I2CID2, 0XFFFF0840
.equ I2CID3, 0XFFFF0844
.equ I2CMSTA_OFFSET, 0X0800
.equ I2CSSTA_OFFSET, 0X0804
.equ I2CSRX_OFFSET, 0X0808
.equ I2CSTX_OFFSET, 0X080C
.equ I2CMRX_OFFSET, 0X0810
.equ I2CMTX_OFFSET, 0X0814
.equ I2CCNT_OFFSET, 0X0818
.equ I2CADR_OFFSET, 0X081C
.equ I2CBYTE_OFFSET, 0X0824
.equ I2CALT_OFFSET, 0X0828
.equ I2CCFG_OFFSET, 0X082C
.equ I2CDIV_OFFSET, 0X0830
.equ I2CID0_OFFSET, 0X0838
.equ I2CID1_OFFSET, 0X083C
.equ I2CID2_OFFSET, 0X0840
.equ I2CID3_OFFSET, 0X0844
@ I2C BUS PERIPHERAL DEVICE 1
.equ I2C0BASE, 0XFFFF0800
.equ I2C0MSTA, 0XFFFF0800
.equ I2C0SSTA, 0XFFFF0804
.equ I2C0SRX, 0XFFFF0808
.equ I2C0STX, 0XFFFF080C
.equ I2C0MRX, 0XFFFF0810
.equ I2C0MTX, 0XFFFF0814
.equ I2C0CNT, 0XFFFF0818
.equ I2C0ADR, 0XFFFF081C
.equ I2C0BYTE, 0XFFFF0824
.equ I2C0ALT, 0XFFFF0828
.equ I2C0CFG, 0XFFFF082C
.equ I2C0DIV, 0XFFFF0830
.equ I2C0ID0, 0XFFFF0838
.equ I2C0ID1, 0XFFFF083C
.equ I2C0ID2, 0XFFFF0840
.equ I2C0ID3, 0XFFFF0844
.equ I2C0MSTA_OFFSET, 0X0800
.equ I2C0SSTA_OFFSET, 0X0804
.equ I2C0SRX_OFFSET, 0X0808
.equ I2C0STX_OFFSET, 0X080C
.equ I2C0MRX_OFFSET, 0X0810
.equ I2C0MTX_OFFSET, 0X0814
.equ I2C0CNT_OFFSET, 0X0818
.equ I2C0ADR_OFFSET, 0X081C
.equ I2C0BYTE_OFFSET, 0X0824
.equ I2C0ALT_OFFSET, 0X0828
.equ I2C0CFG_OFFSET, 0X082C
.equ I2C0DIV_OFFSET, 0X0830
.equ I2C0ID0_OFFSET, 0X0838
.equ I2C0ID1_OFFSET, 0X083C
.equ I2C0ID2_OFFSET, 0X0840
.equ I2C0ID3_OFFSET, 0X0844
@ I2C BUS PERIPHERAL DEVICE 2
.equ I2C1BASE, 0XFFFF0900
.equ I2C1MSTA, 0XFFFF0900
.equ I2C1SSTA, 0XFFFF0904
.equ I2C1SRX, 0XFFFF0908
.equ I2C1STX, 0XFFFF090C
.equ I2C1MRX, 0XFFFF0910
.equ I2C1MTX, 0XFFFF0914
.equ I2C1CNT, 0XFFFF0918
.equ I2C1ADR, 0XFFFF091C
.equ I2C1BYTE, 0XFFFF0924
.equ I2C1ALT, 0XFFFF0928
.equ I2C1CFG, 0XFFFF092C
.equ I2C1DIV, 0XFFFF0930
.equ I2C1ID0, 0XFFFF0938
.equ I2C1ID1, 0XFFFF093C
.equ I2C1ID2, 0XFFFF0940
.equ I2C1ID3, 0XFFFF0944
.equ I2C1MSTA_OFFSET, 0X0900
.equ I2C1SSTA_OFFSET, 0X0904
.equ I2C1SRX_OFFSET, 0X0908
.equ I2C1STX_OFFSET, 0X090C
.equ I2C1MRX_OFFSET, 0X0910
.equ I2C1MTX_OFFSET, 0X0914
.equ I2C1CNT_OFFSET, 0X0918
.equ I2C1ADR_OFFSET, 0X091C
.equ I2C1BYTE_OFFSET, 0X0924
.equ I2C1ALT_OFFSET, 0X0928
.equ I2C1CFG_OFFSET, 0X092C
.equ I2C1DIV_OFFSET, 0X0930
.equ I2C1ID0_OFFSET, 0X0938
.equ I2C1ID1_OFFSET, 0X093C
.equ I2C1ID2_OFFSET, 0X0940
.equ I2C1ID3_OFFSET, 0X0944
@ SERIAL PORT INTERFACE PERIPHERAL
.equ SPIBASE, 0XFFFF0A00
.equ SPISTA, 0XFFFF0A00
.equ SPIRX, 0XFFFF0A04
.equ SPITX, 0XFFFF0A08
.equ SPIDIV, 0XFFFF0A0C
.equ SPICON, 0XFFFF0A10
.equ SPISTA_OFFSET, 0X0A00
.equ SPIRX_OFFSET, 0X0A04
.equ SPITX_OFFSET, 0X0A08
.equ SPIDIV_OFFSET, 0X0A0C
.equ SPICON_OFFSET, 0X0A10
@ PROGRAMABLE LOGIC ARRAY
.equ PLABASE, 0XFFFF0B00
.equ PLAELM0, 0XFFFF0B00
.equ PLAELM1, 0XFFFF0B04
.equ PLAELM2, 0XFFFF0B08
.equ PLAELM3, 0XFFFF0B0C
.equ PLAELM4, 0XFFFF0B10
.equ PLAELM5, 0XFFFF0B14
.equ PLAELM6, 0XFFFF0B18
.equ PLAELM7, 0XFFFF0B1C
.equ PLAELM8, 0XFFFF0B20
.equ PLAELM9, 0XFFFF0B24
.equ PLAELM10, 0XFFFF0B28
.equ PLAELM11, 0XFFFF0B2C
.equ PLAELM12, 0XFFFF0B30
.equ PLAELM13, 0XFFFF0B34
.equ PLAELM14, 0XFFFF0B38
.equ PLAELM15, 0XFFFF0B3C
.equ PLACLK, 0XFFFF0B40
.equ PLAIRQ, 0XFFFF0B44
.equ PLAADC, 0XFFFF0B48
.equ PLADIN, 0XFFFF0B4C
.equ PLADOUT, 0XFFFF0B50
.equ PLAELM0_OFFSET, 0X0B00
.equ PLAELM1_OFFSET, 0X0B04
.equ PLAELM2_OFFSET, 0X0B08
.equ PLAELM3_OFFSET, 0X0B0C
.equ PLAELM4_OFFSET, 0X0B10
.equ PLAELM5_OFFSET, 0X0B14
.equ PLAELM6_OFFSET, 0X0B18
.equ PLAELM7_OFFSET, 0X0B1C
.equ PLAELM8_OFFSET, 0X0B20
.equ PLAELM9_OFFSET, 0X0B24
.equ PLAELM10_OFFSET, 0X0B28
.equ PLAELM11_OFFSET, 0X0B2C
.equ PLAELM12_OFFSET, 0X0B30
.equ PLAELM13_OFFSET, 0X0B34
.equ PLAELM14_OFFSET, 0X0B38
.equ PLAELM15_OFFSET, 0X0B3C
.equ PLACLK_OFFSET, 0X0B40
.equ PLAIRQ_OFFSET, 0X0B44
.equ PLAADC_OFFSET, 0X0B48
.equ PLADIN_OFFSET, 0X0B4C
.equ PLADOUT_OFFSET, 0X0B50
@ GPIO AND SERIAL PORT MUX
.equ GPIOBASE, 0XFFFFF400
.equ GP0CON, 0XFFFFF400
.equ GP1CON, 0XFFFFF404
.equ GP2CON, 0XFFFFF408
.equ GP3CON, 0XFFFFF40C
.equ GP4CON, 0XFFFFF410
.equ GP0DAT, 0XFFFFF420
.equ GP0SET, 0XFFFFF424
.equ GP0CLR, 0XFFFFF428
.equ GP1DAT, 0XFFFFF430
.equ GP1SET, 0XFFFFF434
.equ GP1CLR, 0XFFFFF438
.equ GP2DAT, 0XFFFFF440
.equ GP2SET, 0XFFFFF444
.equ GP2CLR, 0XFFFFF448
.equ GP3DAT, 0XFFFFF450
.equ GP3SET, 0XFFFFF454
.equ GP3CLR, 0XFFFFF458
.equ GP4DAT, 0XFFFFF460
.equ GP4SET, 0XFFFFF464
.equ GP4CLR, 0XFFFFF468
.equ GP0CON_OFFSET, 0X0400
.equ GP1CON_OFFSET, 0X0404
.equ GP2CON_OFFSET, 0X0408
.equ GP3CON_OFFSET, 0X040C
.equ GP4CON_OFFSET, 0X0410
.equ GP0DAT_OFFSET, 0X0420
.equ GP0SET_OFFSET, 0X0424
.equ GP0CLR_OFFSET, 0X0428
.equ GP1DAT_OFFSET, 0X0430
.equ GP1SET_OFFSET, 0X0434
.equ GP1CLR_OFFSET, 0X0438
.equ GP2DAT_OFFSET, 0X0440
.equ GP2SET_OFFSET, 0X0444
.equ GP2CLR_OFFSET, 0X0448
.equ GP3DAT_OFFSET, 0X0450
.equ GP3SET_OFFSET, 0X0454
.equ GP3CLR_OFFSET, 0X0458
.equ GP4DAT_OFFSET, 0X0460
.equ GP4SET_OFFSET, 0X0464
.equ GP4CLR_OFFSET, 0X0468
@ FLASH CONTROL INTERFACE
.equ FLASHBASE, 0XFFFFF800
.equ FEESTA, 0XFFFFF800
.equ FEEMOD, 0XFFFFF804
.equ FEECON, 0XFFFFF808
.equ FEEDAT, 0XFFFFF80C
.equ FEEADR, 0XFFFFF810
.equ FEESIGN, 0XFFFFF818
.equ FEEPRO, 0XFFFFF81C
.equ FEEHIDE, 0xFFFFF820
.equ FEESTA_OFFSET, 0X0800
.equ FEEMOD_OFFSET, 0X0804
.equ FEECON_OFFSET, 0X0808
.equ FEEDAT_OFFSET, 0X080C
.equ FEEADR_OFFSET, 0X0810
.equ FEESIGN_OFFSET, 0X0818
.equ FEEPRO_OFFSET, 0X081C
.equ FEEHIDE_OFFSET, 0x0820
@ PWM
.equ PWMBASE, 0XFFFFFC00
.equ PWMCON, 0XFFFFFC00
.equ PWMSTA0, 0XFFFFFC04
.equ PWMDAT0, 0XFFFFFC08
.equ PWMDAT1, 0XFFFFFC0C
.equ PWMCFG, 0XFFFFFC10
.equ PWMA, 0XFFFFFC14
.equ PWMB, 0XFFFFFC18
.equ PWMC, 0XFFFFFC1C
.equ PWM0, 0XFFFFFC14
.equ PWM1, 0XFFFFFC18
.equ PWM2, 0XFFFFFC1C
.equ PWMEN, 0XFFFFFC20
.equ PWMDAT2, 0XFFFFFC24
.equ PWMSTA1, 0XFFFFFC38
.equ PWMCON_OFFSET, 0X0C00
.equ PWMSTA0_OFFSET, 0X0C04
.equ PWMDAT0_OFFSET, 0X0C08
.equ PWMDAT1_OFFSET, 0X0C0C
.equ PWMCFG_OFFSET, 0X0C10
.equ PWMA_OFFSET, 0X0C14
.equ PWMB_OFFSET, 0X0C18
.equ PWMC_OFFSET, 0X0C1C
.equ PWM0_OFFSET, 0X0C14
.equ PWM1_OFFSET, 0X0C18
.equ PWM2_OFFSET, 0X0C1C
.equ PWMEN_OFFSET, 0X0C20
.equ PWMDAT2_OFFSET, 0X0C24
.equ PWMSTA1_OFFSET, 0X0C38
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