ddc_tb.vhdl.bak

vhdl硬件设计实现一个数字上变频器

LIBRARY ieee  ; 
USE ieee.std_logic_arith.all  ; 
USE ieee.std_logic_1164.all  ; 
ENTITY ddc_tb  IS 
END ddc_tb ; 
 
ARCHITECTURE ddc_tb_arch OF ddc_tb IS
  SIGNAL q_out   :  std_logic_vector (15 downto 0)  ; 
  SIGNAL i_out   :  std_logic_vector (15 downto 0)  ; 
  SIGNAL datin   :  std_logic_vector (15 downto 0)  ; 
  SIGNAL ddc_ena   :  std_logic  ; 
  SIGNAL clk   :  std_logic  ; 
  SIGNAL cout   :  std_logic_vector (1 downto 0)  ; 
  SIGNAL reset   :  std_logic  ; 
  SIGNAL clk_en: std_logic;
  CONSTANT clk_period: TIME:=10 ns;
  
  COMPONENT ddc  
    PORT ( 
           clk       : IN   std_logic;
           ddc_ena   : IN   std_logic;
           reset     : IN   std_logic;
           datin     : IN   std_logic_vector(15 DOWNTO 0);
           I_out        : OUT  std_logic_vector(15 DOWNTO 0);
           Q_out        : OUT  std_logic_vector(15 DOWNTO 0);
           cout         : OUT  std_logic_vector(1 DOWNTO 0)
           );
  END COMPONENT ddc ; 

BEGIN
  DUT  : ddc  
    PORT MAP ( 
      clk   => clk ,
      ddc_ena   => ddc_ena  ,
      reset   => reset  ,
      datin   => datin  ,
      I_out   => I_out ,
      Q_out   => Q_out  ,
      cout  => cout   ) ;
      
    PROCESS BEGIN
        if(clk_en='1')then
            clk<= not clk after (clk_period/2);
        else
           clk<='0';
        end if;
        wait for 40 ns;
        
    END PROCESS; 
  
    process begin
        datain<="1010110100110001";
        clk_en<='0';
        ddc_ena<='0';
        reset<='1';
        wait for 50 ns;
         clk_en<='1';
         ddc_ena<='1';
         reset<='0';
         wait for 100000 ns;
         ddc_ena<='0';
         reset<='1';
         clk_en<='0';
     end process;
  
  PROCESS(clk) 
  BEGIN
     datin<=datain;
     if(clk='0' AND clk'EVENT)then
       datin(15 DOWNTO 0)<= datin(14 DOWNTO 0) & datin(15);
    end if;
  END PROCESS; 
  END ARCHITECTURE;