ddc.vhdl

vhdl硬件设计实现一个数字上变频器

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;




ENTITY ddc IS

	PORT
	(
		   clk       : IN   std_logic;
           ddc_ena   : IN   std_logic;
           reset     : IN   std_logic;
           datin     : IN   std_logic_vector(15 DOWNTO 0);
           I_out        : OUT  std_logic_vector(15 DOWNTO 0);
           Q_out        : OUT  std_logic_vector(15 DOWNTO 0);
           cout         : OUT  std_logic_vector(1 DOWNTO 0)
	);
END ddc  ;
 


    ARCHITECTURE  duc_cos_arch OF ddc  IS



    COMPONENT ddc_counter

       PORT ( 
                   clk    : IN   std_logic;
                   ena    : IN   std_logic;
                   reset  : IN   std_logic;
                   output : OUT  std_logic_vector(1 DOWNTO 0)
             ) ;

    END COMPONENT ;





      SIGNAL  HI: STD_LOGIC :='1';
      SIGNAL  LO: STD_LOGIC :='0';
      SIGNAL  cena: STD_LOGIC;
      SIGNAL  COUN :STD_LOGIC_VECTOR (1  DOWNTO 0);
      SIGNAL  DQOUT :STD_LOGIC_VECTOR (15 downto 0);
      SIGNAL  DIOUT :STD_LOGIC_VECTOR (15 downto 0);


       
     BEGIN 
    	u1: ddc_counter  PORT MAP(clk,cena,reset,COUN);

 
 
    PROCESS(clk)

         BEGIN 
         cout<=COUN;

        IF(ddc_ena=HI) THEN						--cena equalls ddc_ena
         cena<=HI;  
         else
          cena<=LO; 
          END IF;

           IF (clk='1' AND clk'EVENT)THEN			--the modulator rate is 25M,the data rate is 100M,so the data to the cos 1 0 -1 0
           IF(COUN="00" ) THEN
         
                DIOUT<= datin;
             elsif (COUN="01") then
                DIOUT<="0000000000000000";
             elsif (COUN="10") then
                DIOUT<=-signed(datin);
             elsif (COUN="11") then
                DIOUT<="0000000000000000";
             END IF;
          END IF;
          I_out<=DIOUT;

          IF (clk='1' AND clk'EVENT)THEN
           IF(COUN="00" ) THEN
         
                DQOUT<= "0000000000000000";
             elsif (COUN="01") then
                DQOUT<=datin;
             elsif (COUN="10") then
                DQOUT<="0000000000000000";
             elsif (COUN="11") then
                DQOUT<=-signed(datin);
             END IF;
          END IF;
          Q_out<=DQOUT;
   


         END PROCESS;

 
    
       END  duc_cos_arch ;