macreg.h

marvell8385 GSPI开发驱动

// Bit definition for CFMACREG_CCR_CARD_INT_MASK (Card Interrupt Mask)
#define CFMACREG_CCR_CIM_TxDnLdOvr                  W_BIT_0
#define CFMACREG_CCR_CIM_RxUpLdOvr                  W_BIT_1
#define CFMACREG_CCR_CIM_CmdDnLdOvr                 W_BIT_2
#define CFMACREG_CCR_CIM_PwrDown                    W_BIT_3
#define CFMACREG_CCR_CIM_HstEvent                   W_BIT_4
#define CFMACREG_CCR_CIM_MASK                       0x001F

// Define Host to card event code used by CFMACREG_HCR_SCRATCH_PORT
#define CFMACREG_HCR_SP_RxUpLdOvr                   B_BIT_0 // 11/25/02 - Use Scratch pad
//#define CFMACREG_HCR_SP_NONE                        0x00
//#define CFMACREG_HCR_SP_HOST_INIT_IN_PROGRESS       0x01
//#define CFMACREG_HCR_SP_HOST_INIT_FINISHED          0x02
//#define CFMACREG_HCR_SP_HOST_HALT_IN_PROGRESS       0x81

// Scratch register status definitions
// boot loader is ready to begin firmware download
#define CF_SCRATCH_BOOT_WAITING                     0xc3
// Host has completed downloading a 256 byte block
#define CF_SCRATCH_HOST_BLOCK_READY                 0x55
// boot loader as completed moving 256 byte block to memory
#define CF_SCRATCH_BOOT_BLOCK_COMPLETE              0xaa
// Host has finished downloading firmware
#define CF_SCRATCH_HOST_DOWNLOAD_COMPLETE           0x00
// Firmware is up and running
#define CF_SCRATCH_FIRMWARE_READY                   0x5a

#else // SDIO

//
//          Define vendor ID and device ID
//
#define MRVL_PCI_VENDOR_ID                  0x11AB // VID
#define MRVL_8100_PCI_DEVICE_ID             0x1FA4 // DID
#define MRVL_8100_CARDBUS_DEVICE_ID         0x8101

#define MRVL_8100_PCI_REV_0                 0x00
#define MRVL_8100_PCI_REV_1                 0x01
#define MRVL_8100_PCI_REV_2                 0x02
#define MRVL_8100_PCI_REV_3                 0x03
#define MRVL_8100_PCI_REV_4                 0x04
#define MRVL_8100_PCI_REV_5                 0x05
#define MRVL_8100_PCI_REV_6                 0x06
#define MRVL_8100_PCI_REV_7                 0x07
#define MRVL_8100_PCI_REV_8                 0x08
#define MRVL_8100_PCI_REV_9                 0x09
#define MRVL_8100_PCI_REV_a                 0x0a
#define MRVL_8100_PCI_REV_b                 0x0b
#define MRVL_8100_PCI_REV_c                 0x0c
#define MRVL_8100_PCI_REV_d                 0x0d
#define MRVL_8100_PCI_REV_e                 0x0e
#define MRVL_8100_PCI_REV_f                 0x0f

//          The following version information is used bysed by OID_GEN_VENDOR_ID
#define MRVL_8100_PCI_VER_ID               0x00
#define MRVL_8100_CARDBUS_VER_ID           0x01

//
//          Define staiton register offset
//

//          Map to 0x80000000 (Bus control) on BAR4
#define MACREG_REG_H2A_INTERRUPT_CAUSE      0x00000C18 // (From host to ARM)
#define MACREG_REG_H2A_INTERRUPT_MASK       0x00000C1C // (From host to ARM)

#define MACREG_REG_A2H_INTERRUPT_CAUSE      0x00000C88 // (From ARM to host)
#define MACREG_REG_A2H_INTERRUPT_MASK       0x00000C8C // (From ARM to host)

//			Modification on 10/25/02
#define MACREG_REG_A2H_INTERRUPT_MASK_DISABLE 0x00000001  // Bit 0 indicates INT Enable/Disable
                                                          // Bit 0 =1 to Disable

//			Modification on 10/25/02
#define MACREG_REG_A2H_INTERRUPT_CLEAR      0x00000C90 // Write 0 to clear/re-enable interrupt

//          Map to 0x80000000 on BAR4
//#define MACREG_REG_OP_CODE                0x00000000  // Obsolete
#define MACREG_REG_GEN_PTR                  0x00000C68
#define MACREG_REG_INT_CODE                 0x00000C6C
#define MACREG_REG_PPA_BASE                 0x00000C70
#define MACREG_REG_DPA_BASE                 0x00000C74
#define MACREG_REG_RXPDQ_BASE               0x00000C78
#define MACREG_REG_RXPD_RD                  0x00000C7C
#define MACREG_REG_RXPD_WR                  0x00000C80
#define MACREG_REG_WCB_BASE                 0x00000C84
#define MACREG_REG_RSR						0x00000C94

//          (PCI control registers)
#define GT64115_PCI_TIMEOUT                 0x00000C04
#define GT64115_BAR0_REMAP                  0x00000C48
#define GT64115_BAR1_REMAP                  0x00000C4C
#define GT64115_BAR2_REMAP                  0x00000C50
#define GT64115_BAR3_REMAP                  0x00000C54

//          Bit definitio for MACREG_REG_A2H_INTERRUPT_CAUSE (A2HRIC)
#define MACREG_A2HRIC_BIT_MF_INT            0x00000200 // bit 9
#define MACREG_A2HRIC_BIT_MC_INT            0x00000400 // bit 10
#define MACREG_A2HRIC_BIT_SI_INT            0x00000800 // bit 11
#define MACREG_A2HRIC_BIT_GP_INT            0x00001000 // bit 12
#define MACREG_A2HRIC_BIT_CS_INT            0x00002000 // bit 13

#define MACREG_A2HRIC_BIT_DMA0_COMPLETE     0x00008000 // bit 15
#define MACREG_A2HRIC_BIT_DMA1_COMPLETE     0x00010000 // bit 16

#define MACREG_A2HRIC_BIT_TX_DONE           0x01000000 // bit 24
#define MACREG_A2HRIC_BIT_RX_RDY            0x02000000 // bit 25
#define MACREG_A2HRIC_BIT_OPC_DONE          0x04000000 // bit 26
#define MACREG_A2HRIC_BIT_MAC_EVENT         0x08000000 // bit 27
#define MACREG_A2HRIC_BIT_MASK              0x0F000000

//          Bit definitio for MACREG_REG_H2A_INTERRUPT_CAUSE (H2ARIC)
#define MACREG_H2ARIC_BIT_PPA_READY         0x10000000 // bit 28
#define MACREG_H2ARIC_BIT_DOOR_BELL         0x20000000 // bit 29

//          Bit definitio for MACREG_REG_CPU_INTERRUPT_MASK (CIM)
#define MACREG_CIM_BIT_DMA0_COMPLETE_MASK   0x00000010 // bit 4
#define MACREG_CIM_BIT_DMA1_COMPLETE_MASK   0x00000020 // bit 5
#define MACREG_CIM_BIT_DMA2_COMPLETE_MASK   0x00000040 // bit 6
#define MACREG_CIM_BIT_PPA_READY_MASK       0x10000000 // bit 28
#define MACREG_CIM_BIT_DOOR_BELL_MASK       0x20000000 // bit 29

//          Bit definitio for MACREG_REG_PCI_INTERRUPT_MASK (PIM) 
#define MACREG_PIM_BIT_TX_DONE_MASK         0x00400000 // bit 22
#define MACREG_PIM_BIT_RX_RDY_MASK          0x00800000 // bit 23
#define MACREG_PIM_BIT_OPC_DONE_MASK        0x01000000 // bit 24
#define MACREG_PIM_BIT_MAC_EVENT_MASK       0x02000000 // bit 25

//          INT code register event definition
#define MACREG_INT_CODE_TX_PPA_FREE         0x00000000 // Added 05/28/02
#define MACREG_INT_CODE_TX_DMA_DONE         0x00000001
#define MACREG_INT_CODE_LINK_LOSE_W_SCAN    0x00000002
#define MACREG_INT_CODE_LINK_LOSE_NO_SCAN   0x00000003
#define MACREG_INT_CODE_LINK_SENSED         0x00000004
#define MACREG_INT_CODE_CMD_FINISHED        0x00000005
#define MACREG_INT_CODE_MIB_CHANGED         0x00000006 // Added 01/22/02
#define MACREG_INT_CODE_INIT_DONE           0x00000007 // Added 01/30/02
#define MACREG_INT_CODE_DEAUTHENTICATED     0x00000008 // Added 11/08/02
#define MACREG_INT_CODE_DISASSOCIATED       0x00000009 // Added 11/08/02
#define MACREG_INT_CODE_PS_AWAKE			0x0000000a
#define MACREG_INT_CODE_PS_SLEEP			0x0000000b
#define MACREG_INT_CODE_TX_DONE				0x0000000c
//Mic error++
#define MACREG_INT_CODE_WPA_MIC_ERR_UNICAST     0x0000000d
#define MACREG_INT_CODE_WPA_MIC_ERR_MULTICAST   0x0000000e       
//Mic error--
#define MACREG_INT_CODE_HOST_AWAKE              0x0000000f
#define MACREG_INT_CODE_DS_AWAKE                0x00000010 //Deep Sleep Awake
#define MACREG_INT_CODE_ADHOC_BCN_LOST          0x00000011
#ifdef HOST_SLEEP
#define MACREG_INT_CODE_HOST_SLEEP_AWAKE		0x00000012 
#endif

#endif // CF-DRIVER - SDIO
#define MACREG_INT_CODE_RSSI_LOW                    0x00000019
#define MACREG_INT_CODE_RSSI_HIGH                   0x0000001c

/*
===============================================================================
                            PUBLIC TYPE DEFINITIONS
===============================================================================
*/

#else
#endif // __MACREG_H_