📄 oid.h
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/******************* ?Marvell Semiconductor, Inc., 2004 ********************
*
* Purpose:
*
* Structure and constant definition for custome OID supported by
* the driver
*
* Notes:
*
* $Author: xiaojie $
*
* $Date: 2006/07/18 11:11:41 $
*
* $Revision: 1.1 $
*
*****************************************************************************/
#ifndef _MRVL_OID_H_
#define _MRVL_OID_H_
#ifndef NDIS_OID
typedef ULONG NDIS_OID, *PNDIS_OID;
#endif
//
//
// IEEE 802.11 OIDs
//
#define OID_802_11_BSSID 0x0D010101
#define OID_802_11_SSID 0x0D010102
#define OID_802_11_NETWORK_TYPES_SUPPORTED 0x0D010203
#define OID_802_11_NETWORK_TYPE_IN_USE 0x0D010204
#define OID_802_11_TX_POWER_LEVEL 0x0D010205
#define OID_802_11_RSSI 0x0D010206
#define OID_802_11_RSSI_TRIGGER 0x0D010207
#define OID_802_11_INFRASTRUCTURE_MODE 0x0D010108
#define OID_802_11_FRAGMENTATION_THRESHOLD 0x0D010209
#define OID_802_11_RTS_THRESHOLD 0x0D01020A
#define OID_802_11_NUMBER_OF_ANTENNAS 0x0D01020B
#define OID_802_11_RX_ANTENNA_SELECTED 0x0D01020C
#define OID_802_11_TX_ANTENNA_SELECTED 0x0D01020D
#define OID_802_11_SUPPORTED_RATES 0x0D01020E
#define OID_802_11_DESIRED_RATES 0x0D010210
#define OID_802_11_CONFIGURATION 0x0D010211
#define OID_802_11_STATISTICS 0x0D020212
#define OID_802_11_ADD_WEP 0x0D010113
#define OID_802_11_REMOVE_WEP 0x0D010114
#define OID_802_11_DISASSOCIATE 0x0D010115
#define OID_802_11_POWER_MODE 0x0D010216
#define OID_802_11_BSSID_LIST 0x0D010217
#define OID_802_11_AUTHENTICATION_MODE 0x0D010118
#define OID_802_11_PRIVACY_FILTER 0x0D010119
#define OID_802_11_BSSID_LIST_SCAN 0x0D01011A
#define OID_802_11_WEP_STATUS 0x0D01011B
#define OID_802_11_RELOAD_DEFAULTS 0x0D01011C
// ****************************************************************************
// Marvel specific OIDs
//
#define OID_MRVL_OEM_GET_ULONG 0xff010201
#define OID_MRVL_OEM_SET_ULONG 0xff010202
#define OID_MRVL_OEM_GET_STRING 0xff010203
#define OID_MRVL_OEM_COMMAND 0xff010204
// set the region code
// the setting is permanently written into card's EEPROM
#define OID_MRVL_REGION_CODE 0xff010205
#define OID_MRVL_RADIO_PREAMBLE 0xff010206
#define OID_MRVL_BSSID_SCAN 0xff010207
#define OID_MRVL_SSID_SCAN 0xff010208
// set the RF channel
// can only be accessed when not associated, SET only
// Information buffer should contain the channel number
#define OID_MRVL_RF_CHANNEL 0xff010209
#define OID_MRVL_WIRELESS_MODE 0xff01020a
#define OID_MRVL_CHIP_VERSION 0xff01020b
// access Baseband register
#define OID_MRVL_BBP_REG 0xff01020c
// access MAC register
#define OID_MRVL_MAC_REG 0xff01020d
// access RF register
#define OID_MRVL_RF_REG 0xff01020e
// access flash memory
#define OID_MRVL_EEPROM_ACCESS 0xff01020f
// send manufacture command
//#define OID_MRVL_MFG_COMMAND 0xff010210
// program the MAC address in the EEPROM
// driver and firmware will also update the MAC address
#define OID_MRVL_MAC_ADDRESS 0xFF010210
// put the card into TX mode
// can only be accessed when not associated, SET Only
#define OID_MRVL_TX_MODE 0xFF010211
// put the card into RX mode
// can only be accessed when not associated, SET only
#define OID_MRVL_RX_MODE 0xFF010212
// L2 romaing OID
#define OID_MRVL_L2ROAMING 0XFF010213
// LED control, set only
// Controls the behavior of the LED
#define OID_MRVL_LED_CONTROL 0xFF010214
// Multiple dtim value, set only
// Number of DTIM to sleep
#define OID_MRVL_MULTIPLE_DTIM 0xFF010215
#ifdef MRVL_SET_RF_RADIO
#define OID_MRVL_ENABLE_RADIO 0xFF010217
#define OID_MRVL_DISABLE_RADIO 0xFF010218
#define OID_MRVL_RADIO_CONTROL 0xFF010219
#endif
#ifdef DEEP_SLEEP
#define OID_MRVL_DEEP_SLEEP 0xff010220
#endif
#ifdef ADHOCAES
#define OID_MRVL_REMOVE_ADHOCAES 0xff010221
#define OID_MRVL_SET_ADHOCAES 0xff010222
#define OID_MRVL_GET_ADHOCAES 0xff010223
#endif
#ifdef HOST_SLEEP
#define OID_MRVL_HOST_SLEEP_CFG 0xff010224
#define OID_MRVL_WAKEUP_DEVICE 0xff01023A
#endif //HOST_WAKEUP
#define OID_MRVL_SLEEP_PARAMS 0xff010225
#ifdef WMM
#define OID_MRVL_WMM_STATE 0xff010234
#define OID_MRVL_WMM_ACK_POLICY 0xff010235
#define OID_MRVL_WMM_STATUS 0xff010236
#ifdef WMM_UAPSD
#define OID_MRVL_SLEEP_PERIOD 0xff010237
#endif
#endif //WMM
#ifdef HOST_SLEEP_SYNC_PS
#define OID_MRVL_HOST_WAKE_UP_SYNC_PS 0xff010230
#endif
#define OID_MRVL_FW_WAKE_METHOD 0xff010231
#define OID_MRVL_INACTIVITY_TIMEOUT 0xff010232
////////////////////////////////////////////////////////////////
// Information buffer should point to one of the following
// data structure
////////////////////////////////////////////////////////////////
typedef struct _OID_MRVL_DS_BBP_REGISTER_ACCESS
{
NDIS_OID Oid;
USHORT usOffset;
ULONG ulValue;
} OID_MRVL_DS_BBP_REGISTER_ACCESS, *POID_MRVL_DS_BBP_REGISTER_ACCESS;
typedef struct _OID_MRVL_DS_RF_REGISTER_ACCESS
{
NDIS_OID Oid;
USHORT usOffset;
ULONG ulValue;
} OID_MRVL_DS_RF_REGISTER_ACCESS, *POID_MRVL_DS_RF_REGISTER_ACCESS;
typedef struct _OID_MRVL_DS_MAC_REGISTER_ACCESS
{
NDIS_OID Oid;
USHORT usOffset;
ULONG ulValue;
} OID_MRVL_DS_MAC_REGISTER_ACCESS, *POID_MRVL_DS_MAC_REGISTER_ACCESS;
typedef struct _OID_MRVL_DS_EEPROM_ACCESS
{
NDIS_OID Oid;
USHORT usDataLength;
ULONG ulAddress;
UCHAR pData[1];
} OID_MRVL_DS_EEPROM_ACCESS, *POID_MRVL_DS_EEPROM_ACCESS;
#ifdef ENABLE_802_11D
typedef struct _OID_MRVL_DS_REGION_CODE
{
//dralee 081005, V4
//NDIS_OID Oid;
//ULONG ulRegionCode;
ULONG bIsEnable;
USHORT usRegionCode; // country code
USHORT usBand; // b:
} OID_MRVL_DS_REGION_CODE, *POID_MRVL_DS_REGION_CODE;
#endif
typedef struct _OID_MRVL_DS_MAC_ADDRESS
{
NDIS_OID Oid;
UCHAR EthAddr[6];
} OID_MRVL_DS_MAC_ADDRESS, *POID_MRVL_DS_MAC_ADDRESS;
typedef struct _OID_DS_MRVL_RF_CHANNEL
{
NDIS_OID Oid;
ULONG ulChannelNumber;
} OID_MRVL_DS_RF_CHANNEL, *POID_MRVL_DS_RF_CHANNEL;
#ifdef MRVL_SET_OID_POWERMODE
typedef struct _OID_DS_MRVL_POWER_SAVE_MODE
{
NDIS_OID Oid;
ULONG pPowerSaveMode[1];
} OID_MRVL_DS_POWER_SAVE_MODE, *POID_MRVL_DS_POWER_SAVE_MODE;
#endif
#ifdef MRVL_SET_RF_RADIO
typedef struct _OID_DS_MRVL_RF_RADIO
{
NDIS_OID Oid;
UCHAR RADIO;
} OID_DS_MRVL_RF_RADIO, * POID_DS_MRVL_RF_RADIO;
#endif
// OID_MRVL_TX_Mode Mode values
#define TX_MODE_NORMAL 0
#define TX_MODE_CONT 1
#define TX_MODE_CW 2
#define TX_MODE_MAX 3 // not a valid value, used as a upper limit
typedef struct _OID_MRVL_DS_TX_MODE
{
NDIS_OID Oid;
ULONG ulMode;
} OID_MRVL_DS_TX_MODE, *POID_MRVL_DS_TX_MODE;
// OID_MRVL_RX_Mode Mode values
#define RX_MODE_NORMAL 0
#define RX_MODE_RDONLY 1
#define RX_MODE_MAX 2 // not a valid value, used as a upper limit
typedef struct _OID_DS_MRVL_RX_MODE
{
NDIS_OID Oid;
ULONG ulMode;
} OID_MRVL_DS_RX_MODE, *POID_MRVL_DS_RX_MODE;
// L2 Roaming data structure
typedef struct _OID_MRVL_DS_L2ROAMING
{
NDIS_OID Oid;
UCHAR Mode; // Off, Fixed level roaming, or auto level roaming
UCHAR Delta; // Delta from the original AP RSSI used for switching
// between 0-100. For example if 80% is desired, use 80
ULONG Period; // number of seconds between each period
} OID_MRVL_DS_L2ROAMING, *POID_MRVL_DS_L2ROAMING;
// Mode definition for OID_MRVL_DS_L2ROAMING
#define MRVL_L2ROAMING_MODE_OFF 0
#define MRVL_L2ROAMING_MODE_FIXED 1 // user picks the delta
#define MRVL_L2ROAMING_MODE_AUTO 2 // driver picks the delta
// minmum roaming period is 30 seconds
#define MRVL_L2ROAMING_MIN_PERIOD 30
#if 0 //tt ++ v5 firmware
typedef struct _OID_MRVL_DS_LED_CONTROL
{
NDIS_OID Oid;
ULONG GpioNum; // GPIO number for LED(=0, 0-7)
ULONG LedCycle; // LED Cycle: 0-5, or ON/OFF
ULONG DutyCycle; // LED Duty Cycle: 0-4
} OID_MRVL_DS_LED_CONTROL, *POID_MRVL_DS_LED_CONTROL;
#endif //0 //tt -- firmware
// Define LED cycles
#define MRVL_LED_CONTROL_LED_CYCLE_37MS 0x0
#define MRVL_LED_CONTROL_LED_CYCLE_74MS 0x1
#define MRVL_LED_CONTROL_LED_CYCLE_149MS 0x2
#define MRVL_LED_CONTROL_LED_CYCLE_298MS 0x3
#define MRVL_LED_CONTROL_LED_CYCLE_596MS 0x4
#define MRVL_LED_CONTROL_LED_CYCLE_1192MS 0x5
#define MRVL_LED_CONTROL_LED_ON 0xfffd /* LED ON */
#define MRVL_LED_CONTROL_LED_OFF 0xffff /* LED OFF */
/*
Define LED duty cycles
*/
#define MRVL_LED_CONTROL_LED_DUTY_CYCLE_2 0x0 /* 1/2 */
#define MRVL_LED_CONTROL_LED_DUTY_CYCLE_4 0x1 /* 1/4 */
#define MRVL_LED_CONTROL_LED_DUTY_CYCLE_8 0x2 /* 1/8 */
#define MRVL_LED_CONTROL_LED_DUTY_CYCLE_16 0x3 /* 1/16 */
#define MRVL_LED_CONTROL_LED_DUTY_CYCLE_32 0x4 /* 1/32 */
typedef struct _OID_MRVL_DS_MULTIPLE_DTIM
{
NDIS_OID Oid;
#ifdef MRVL_USE_MULTIPLE_DTIM
USHORT DtimNum;
#else
UCHAR DtimNum; /* multiple of DTIM from AP */
#endif
} OID_MRVL_DS_MULTIPLE_DTIM, *POID_MRVL_DS_MULTIPLE_DTIM;
#ifdef DEEP_SLEEP
typedef struct _OID_MRVL_DS_DEEP_SLEEP
{
ULONG ulEnterDeepSleep;
} OID_MRVL_DS_DEEP_SLEEP, *POID_MRVL_DS_DEEP_SLEEP;
#endif
#ifdef HOST_SLEEP
typedef struct _OID_MRVL_DS_HOST_SLEEP_CFG
{
ULONG ulCriteria;
UCHAR ucGPIO;
UCHAR ucGap;
} OID_MRVL_DS_HOST_SLEEP_CFG, *POID_MRVL_DS_HOST_SLEEP_CFG;
#endif
/*
#ifdef HOST_SLEEP_SYNC_PS
#define HOST_SLEEP_SYNC_WITH_DEVICE_PS 0x1
#define HOST_SLEEP_NOT_SYNC_WITH_DEVICE_PS 0x0
#endif
*/
#pragma pack(1)
typedef struct _OID_MRVL_DS_SLEEP_PARAMS
{
USHORT Error;
USHORT Offset;
USHORT StableTime;
UCHAR CalControl;
UCHAR ExternalSleepClk;
USHORT Reserved;
} OID_MRVL_DS_SLEEP_PARAMS, *POID_MRVL_DS_SLEEP_PARAMS;
/*
#ifdef HOST_SLEEP_SYNC_PS
typedef struct _OID_MRVL_DS_SLEEP_SYNC_PS
{
USHORT smode;
} OID_MRVL_DS_SLEEP_SYNC_PS, *POID_MRVL_DS_SLEEP_SYNC_PS;
#endif
*/
typedef struct _OID_MRVL_DS_FW_WAKE_METHOD
{
USHORT method;
} OID_MRVL_DS_FW_WAKE_METHOD, *POID_MRVL_DS_FW_WAKE_METHOD;
typedef struct _OID_MRVL_INACTIVITY_TIMEOUT
{
USHORT time;
} OID_MRVL_DS_INACTIVITY_TIMEOUT, *POID_MRVL_DS_INACTIVITY_TIMEOUT;
#ifdef WMM
typedef struct _OID_MRVL_DS_WMM_STATE
{
UCHAR State;
}OID_MRVL_DS_WMM_STATE, *POID_MRVL_DS_WMM_STATE;
typedef struct _OID_MRVL_DS_WMM_ACK_POLICY
{
UCHAR AC;
UCHAR AckPolicy;
}OID_MRVL_DS_WMM_ACK_POLICY, *POID_MRVL_DS_WMM_ACK_POLICY;
typedef struct _OID_MRVL_DS_WMM_AC_STATUS
{
WMM_AC_STATUS Status[4];
}OID_MRVL_DS_WMM_AC_STATUS, *POID_MRVL_DS_WMM_AC_STATUS;
typedef struct _OID_MRVL_DS_WAKEUP_DEVICE
{
UCHAR wake;
}OID_MRVL_DS_WAKEUP_DEVICE, *POID_MRVL_DS_WAKEUP_DEVICE;
#ifdef WMM_UAPSD
typedef struct _OID_MRVL_DS_WMM_SLEEP_PERIOD
{
USHORT period;
}OID_MRVL_DS_WMM_SLEEP_PERIOD, *POID_MRVL_DS_WMM_SLEEP_PERIOD;
#endif //WMM_UAPSD
#endif //WMM
#pragma pack()
//tt ++ v5 firmware
#define OID_MRVL_TPC_CFG 0xff010226
#define OID_MRVL_PWR_CFG 0xff010227
#define OID_MRVL_RATE_ADAPT_RATESET 0xff010233
typedef struct _OID_MRVL_DS_LED_CONTROL
{
NDIS_OID Oid;
USHORT NumLed;
UCHAR data[256]; //TLV format
} OID_MRVL_DS_LED_CONTROL, *POID_MRVL_DS_LED_CONTROL;
#ifdef CAL_DATA
#define OID_MRVL_CAL_DATA 0xff010228
#define OID_MRVL_CAL_DATA_EXT 0xff010229
typedef struct _OID_MRVL_DS_CAL_DATA
{
NDIS_OID Oid;
UCHAR Reserved1[9];
UCHAR PAOption; /* PA calibration options */
UCHAR ExtPA; /* type of external PA */
UCHAR Ant; /* Antenna selection */
USHORT IntPA[14]; /* channel calibration */
UCHAR PAConfig[4]; /* RF register calibration */
UCHAR Reserved2[4];
USHORT Domain; /* Regulatory Domain */
UCHAR ECO; /* ECO present or not */
UCHAR LCT_cal; /* VGA capacitor calibration */
UCHAR Reserved3[12];
} OID_MRVL_DS_CAL_DATA, *POID_MRVL_DS_CAL_DATA;
typedef struct _OID_MRVL_DS_CAL_DATA_EXT
{
NDIS_OID Oid;
USHORT Revision;
USHORT CalDataLen;
UCHAR CalData[1024];
} OID_MRVL_DS_CAL_DATA_EXT, *POID_MRVL_DS_CAL_DATA_EXT;
#endif //CAL_DATA
typedef struct _OID_MRVL_DS_PWR_CFG
{
NDIS_OID Oid;
UCHAR Enable;
UCHAR P0;
UCHAR P1;
UCHAR P2;
} OID_MRVL_DS_PWR_CFG, *POID_MRVL_DS_PWR_CFG;
typedef struct _OID_MRVL_DS_TPC_CFG
{
NDIS_OID Oid;
UCHAR Enable;
UCHAR P0;
UCHAR P1;
UCHAR P2;
UCHAR UseSNR;
} OID_MRVL_DS_TPC_CFG, *POID_MRVL_DS_TPC_CFG;
typedef struct _OID_MRVL_DS_RATE_ADAPT_RATESET
{
NDIS_OID Oid;
USHORT EnableHwAuto; // 1: enable
USHORT Bitmap;
} OID_MRVL_DS_RATE_ADAPT_RATESET, *POID_MRVL_DS_RATE_ADAPT_RATESET;
typedef struct _OID_MRVL_DS_SUBSCRIBE_EVENT
{
NDIS_OID Oid;
USHORT Events;
} OID_MRVL_DS_SUBSCRIBE_EVENT, *POID_MRVL_DS_SUBSCRIBE_EVENT;
//tt --
#endif // _MRVL_OID_H_
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