spi.h

marvell8385 GSPI开发驱动

/******************** (c) Marvell Semiconductor, Inc., 2003 *******************
 *
 * $Header:
 *
 * Purpose:
 *    This file contains the function prototypes and definitions for the
 *    spi.c.
 *
 * Public Procedures:
 *
 * Notes:
 *    None.
 *
 *****************************************************************************/

#ifdef IF_SPI

#ifndef _SPI_H_
#define _SPI_H_

#include "eagledev.h"

typedef enum {
	MVMS_DAT = 0,
	MVMS_CMD = 1,
	MVMS_TXDONE = 2,
	MVMS_EVENT
} mv_ms_type;

#define SPI_API_STATUS int
#define SD_API_STATUS int
#define SD_API_STATUS_SUCCESS 0

#define SD_API_SUCCESS(x) ((x)==0)

//=============================================================================
//                                Special DEFINITIONS
//=============================================================================

#define GSPI_WRITE 0x8000
#define u8	UCHAR
#define u16	USHORT
#define u32   UINT

#define CMD_READBASE_REG		0x10
#define CMD_WRITEBASE_REG		0x14
#define CMD_RDWRPORT_REG		0x18

#define DATA_READBASE_REG		0x1C
#define DATA_WRITEBASE_REG	0x20
#define DATA_RDWRPORT_REG		0x24

#define SCRATCH_1_REG			0x28
#define SCRATCH_2_REG			0x2C
#define SCRATCH_3_REG			0x30
#define SCRATCH_4_REG			0x34

#define HOST_INT_CTRL_REG		0x40

#define CARD_INT_CAUSE_REG		0x44
#define CARD_INT_STATUS_REG		0x48
#define CARD_INT_EVENT_REG		0x4A
#define CARD_INT_EVENT_MASK_REG		0x4C
#define CARD_INT_STATUS_MASK_REG	0x50
#define CARD_INT_RESET_SELECT_REG	0x54

#define HOST_INT_CAUSE_REG		0x58
#define HOST_INT_STATUS_REG		0x5C
#define HOST_INT_EVENT_REG		0x5E
#define HOST_INT_EVENT_MASK_REG		0x60
#define HOST_INT_STATUS_MASK_REG	0x64
#define HOST_INT_RESET_SELECT_REG	0x68

/* Bit definition for CARD_INT_CAUSE (Card Interrupt Cause) */
#define CIC_TxDnLdOvr			B_BIT_0
#define CIC_RxUpLdOvr			B_BIT_1
#define CIC_CmdDnLdOvr			B_BIT_2
#define CIC_HostEvent			B_BIT_3
#define CIC_CmdUpLdOvr			B_BIT_4
#define CIC_PwrDown			B_BIT_5

#define HIS_MASK				0xFF
#define HIS_TxDnLdRdy			B_BIT_0
#define HIS_RxUpLdRdy			B_BIT_1
#define HIS_CmdDnLdRdy			B_BIT_2
#define HIS_CardEvent			B_BIT_3
#define HIS_CmdUpLdRdy			B_BIT_4
#define HIS_WrFifoOvrflow		B_BIT_5
#define HIS_RdFifoUndrflow		B_BIT_6
#define HIS_WlanReady			B_BIT_7


#define HIC_DEFAULT_VALUE 0
/* Bit definition for HOST_INT_CTRL_REG (Host Interrupt Control) */
#define HIC_WakeUp			B_BIT_0
#define HIC_WlanRdy			B_BIT_1
#define HIC_TxDnldAuto			B_BIT_5
#define HIC_RxUpldAuto			B_BIT_6
#define HIC_CmdDnldAuto			B_BIT_7
#define HIC_CmdUpldAuto			B_BIT_8


// match with SDIO driver
#define DOWNLOAD_HOST_INT_STATUS_RDY	B_BIT_0

/* Value to check once the firmware is downloaded */
#define FIRMWARE_DNLD_OK 		0x88888888


// block size of FW download
#define SPI_FW_DOWNLOAD_PKTCNT 64
 #define FIRMWARE_DNLD_END 		0x0000

//=============================================================================
//                                DEFINITIONS
//=============================================================================


#define MRVL_8100_SPI_VER_ID           0x02 // TODO: what should this be?

// amount of time to wait in ms to check FW again if it is not ready
#define SPI_FW_NOT_READY_WAIT_TIME     5

#define CF_READ_CMD_BUF_SIZE 128
#define CF_WRITE_CMD_BUF_SIZE 128

#define SPI_EXTENDED_IO_BLOCK_SIZE	 32  //256  //128	//512  //32

#define SPI_IO_READY               0x08
#define SPI_CIS_CARD_READY         0x04
#define SPI_UPLOAD_CARD_READY      0x02
#define SPI_DOWNLOAD_CARD_READY    0x01
#define SPI_IO_PORT                0x10000

#ifdef PWARE_SPI_INTR_MODIFICATIONS
	#define SPI_DISABLE_INTERRUPT_MASK 0x01
	#define SPI_ENABLE_INTERRUPT_MASK  0x00
#else
	#define SPI_DISABLE_INTERRUPT      0x0
	#define SPI_ENABLE_INTERRUPT       0x1
#endif // PWARE_SDIO_INTR_MODIFICATIONS

#define UPLOAD_HOST_INT_STATUS_RDY      B_BIT_1

#ifndef MRV_CHIP_8305
#define UPLOADDOWNLOAD_HOST_INT_STATUS_RDY 0x03
#endif

// host control register
#define HCR_HOST_INT_STATUS_REGISTER        0x5C
//#define HCR_HOST_INT_STATUS_RSR_REGISTER    0x6
//#define HCR_HOST_INT_MASK_REGISTER          0x4
//#define HCR_HOST_CONFIGURATION_REGISTER     0x3

//#ifndef MRV_CHIP_8305
//#define CARD_REVISION_REG            0x3c
//#endif

// card control register
//#define CCR_CARD_STATUS_REGISTER        0x20

//#define LENGTH_SCRATCH_REGISTER                         0x80FE
#define PACKET_TYPE_MAC_EVENT_SCRATCH_REGISTER          0x80FC

// code which will be in the scratch register after FW is initialized
#define SPI_FW_INIT_CODE               0xFEDC

// 50 ms wait time
#define PKT_WAIT_TIME               50000   // number of 10 us units

enum spi_pkt_type {
   SPI_DATA_PKT = 0,
   SPI_CMD_PKT,
   SPI_TX_DONE_EVENT,
   SPI_MAC_EVENT
};

enum sdio_pkt_type {
   SDIO_DATA_PKT = 0,
   SDIO_CMD_PKT,
   SDIO_TX_DONE_EVENT,
   SDIO_MAC_EVENT
};


// 050505, begin
// Structure describing Registry values
//typedef struct _REG_VALUE_DESCR {
//    LPWSTR val_name;
//    DWORD  val_type;
//    PBYTE  val_data;
//	} REG_VALUE_DESCR, *PREG_VALUE_DESCR;
// 050505, end
#define NOT !

extern int g_spi_dummy_clk_reg;
extern int	 g_spi_dummy_clk_data;
extern USHORT  dummy_clk_reg;
extern USHORT  dummy_clk_data;


//=============================================================================
//                          PUBLIC TYPE DEFINITIONS
//=============================================================================
//
//

//=============================================================================
//                          FUNCTION HEADER
//=============================================================================
///crlo:modify ++
///extern int spi_init(void);
extern int spi_init(PMRVDRV_ADAPTER Adapter);
///crlo:modify --
extern void gspi_reset(void);
extern void sbi_disable_host_int(void);
extern void sbi_enable_host_int(void);
extern int gspi_read_reg16(u16 reg, u16 *data);
extern int gspi_write_reg(u16 reg, u16 data);
#if PXA270_SPI
int gspi_read_intstatue();
#endif ///PXA270_SPI
extern IF_FW_STATUS spi_IsFirmwareLoaded(IN PMRVDRV_ADAPTER pAdapter);
extern IF_FW_STATUS spi_FirmwareDownload(IN PMRVDRV_ADAPTER Adapter);
extern IF_FW_STATUS spi_FirmwareDownload_reboot(IN PMRVDRV_ADAPTER Adapter);
extern SD_API_STATUS SPIDownloadPkt(
	IN PMRVDRV_ADAPTER   Adapter,
	IN PSDIO_TX_PKT      pDownloadPkt
);
extern IF_API_STATUS spi_GetLengthOfDataBlock( PMRVDRV_ADAPTER Adapter, USHORT *pLength );
extern int sbi_card_to_host(u32 type, u8 *payload);
extern void gspi_read_data_direct(u8 *data, u16 reg, u16 size);

extern void EnableInterrupt(PMRVDRV_ADAPTER Adapter);
extern VOID DisableInterrupt(IN PMRVDRV_ADAPTER Adapter);
extern IF_API_STATUS sbi_exit_deep_sleep(void);
extern IF_API_STATUS sbi_exit_deep_sleep_clean(void);

#endif // _SPI_H_

#endif // SPI