📄 mfrc500.lst
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565 /********************************
566 * set mfrc500 receive gain *
567 ********************************/
568 void M500SetRcvGain(uchar gain)
569 {
570 1 if(gain > 3)
571 1 gain = 3;
572 1 RxGain = gain + 0x70;
573 1
574 1 WriteIO(RegRxControl1, RxGain);//73:42db, 72:38, 71:30, 70:27
575 1 M500PcdRfReset(5);
576 1 }
577
578 /********************************
579 * init mfrc500 *
580 ********************************/
581 uchar M500PcdInit(void)
582 {
583 1 uchar miret = MI_OK;
584 1
585 1 IT0 = 1; // edge
586 1
587 1 SetIntPri(IE0_VECTOR, 2);
588 1
589 1 miret = M500PcdReset();
590 1 #ifdef FORCE_RESET
if(miret != MI_OK)
return miret;
#endif
594 1
595 1 WriteIO(RegClockQControl,0x00);
596 1 WriteIO(RegClockQControl,0x40);
597 1 SoftDelayCyl(100);
598 1 ClearBitMask(RegClockQControl,0x40); ////
599 1 // WriteIO(RegTxControl, 0x5b);//////////////////////////////////
600 1
601 1 // The following values for RegBitPhase and
602 1 // RegRxThreshold represents an optimal
603 1 // value for our demo package. For user
604 1 // implementation some changes could be
605 1 // necessary
606 1 // initialize bit phase
607 1 WriteIO(RegBitPhase,0xAD);
608 1
609 1 // initialize minlevel
610 1 WriteIO(RegRxThreshold,0xFF);
C51 COMPILER V8.00 MFRC500 04/23/2009 15:56:15 PAGE 11
611 1
612 1 // disable auto power down
613 1 //WriteIO(RegRxControl2,0x01);
614 1 WriteIO(RegRxControl2,0x01);//C1 for Power saving, 01 for disable auto power down
615 1 //WriteIO(RegDecoderControl,0x28);/////////////////////////////////////////////
616 1 WriteIO(RegRxControl1,RxGain);//73:42db, 72:38, 71:30, 70:27///////////////////
617 1
618 1
619 1 // Depending on the processing speed of the
620 1 // operation environment, the waterlevel
621 1 // can be adapted. (not very critical for
622 1 // mifare applications)
623 1 // initialize waterlevel to value 4
624 1 WriteIO(RegFIFOLevel,0x1a); // 4 // 1a
625 1
626 1 //Timer configuration
627 1 WriteIO(RegTimerControl,0x02); // TStopRxEnd=0,TStopRxBeg=0, 2
628 1 // TStartTxEnd=1,TStartTxBeg=0
629 1 // timer must be stopped manually
630 1
631 1 WriteIO(RegIRqPinConfig,0x03); // interrupt active low enable
632 1
633 1
634 1 M500PcdRfReset(5); // Rf - reset and enable output driver //1-2
635 1
636 1 return miret;
637 1 /*
638 1 //芯片可配置选项
639 1 WriteIO(RegClockQControl,0x0);
640 1 WriteIO(RegClockQControl,0x40);
641 1 delay(2);// wait approximately 50ms(>100us) - calibration in progress
642 1 //ClearBitMask(RegClockQControl,0x40); // clear bit ClkQCalib for further calibration
643 1 WriteIO(RegBitPhase,0xAD);// initialize bit phase
644 1 WriteIO(RegRxThreshold,0xFF);// initialize minlevel
645 1 //WriteIO(RegRxControl2,01);// disable auto power down
646 1 WriteIO(RegTimerControl,0x0a);//TStartTxEnd=1,TStopRxEnd=1
647 1 WriteIO(RegIRqPinConfig,0x3); // interrupt active low enable
648 1 ClearBitMask(RegTxControl,0x03); // Tx2RF-En, Tx1RF-En disable
649 1 delay(2); // Delay for 1 ms
650 1 WriteIO(RegTxControl,0x5b);
651 1 WriteIO(RegRxControl1,0x72);//38db
652 1 WriteIO(RegRxControl2,0xC1);//41);//Power saving
653 1 WriteIO(RegDecoderControl,0x28);
654 1 WriteIO(RegTimerClock,0x07);
655 1 WriteIO(RegRxThreshold,0xff);////
656 1 WriteIO(RegFIFOLevel,0x01);///
657 1 //初始状态
658 1 WriteIO(RegInterruptRq,0x7F);//clear all inter
659 1 //WriteIO(RegInterruptEn,0xFF);//enable all interrupts
660 1 WriteIO(RegCommand,PCD_IDLE);
661 1 SetBitMask(RegControl,0x01);//FlushFIFO
662 1 SetBitMask(RegControl,0x04);//StopTimer
663 1 WriteIO(RegInterruptEn,0x7f);
664 1 WriteIO(RegInterruptEn,0x88);//RC500只开接收中断
665 1 */
666 1 }
667
668 /********************************
669 * mfrc500 reset *
670 * ms: time between clr and set *
671 ********************************/
672 void M500PcdRfReset(uchar ms)
C51 COMPILER V8.00 MFRC500 04/23/2009 15:56:15 PAGE 12
673 {
674 1 ClearBitMask(RegTxControl,0x03);
675 1
676 1 if(ms > 0)
677 1 {
678 2 delay(ms + 1);
679 2 SetBitMask(RegTxControl,0x03);
680 2 }
681 1 }
682
683 uchar M500PcdReset(void)
684 {
685 1 unsigned int starttime;
686 1 unsigned char rdval = 0;
687 1
688 1 // first reset by the rst pin
689 1 M500Reset();
690 1
691 1 // wait until reset command recognized
692 1 starttime = GetTickCount();
693 1 while (ReadRawIO(RegCommand) & 0x3F != 0x3F)
694 1 {
695 2 if(GetTickCount() - starttime >= 200)
696 2 {
697 3 #ifndef FORCE_RESET
698 3 return MI_RESETERR;
699 3 #else
rdval = MI_RESETERR;
break;
#endif
703 3 }
704 2 }
705 1
706 1 // while reset sequence in progress
707 1 starttime = GetTickCount();
708 1 while (ReadRawIO(RegCommand) & 0x3F)
709 1 {
710 2 if(GetTickCount() - starttime >= 200)
711 2 {
712 3 #ifndef FORCE_RESET
713 3 return MI_RESETERR;
714 3 #else
rdval = MI_RESETERR;
break;
#endif
718 3 }
719 2 }
720 1
721 1 WriteRawIO(RegPage,0x80); // Dummy access in order to determine the bus
722 1 // configuration
723 1 // necessary read access
724 1 // after first write access, the returned value
725 1 // should be zero ==> interface recognized
726 1 if (ReadRawIO(RegCommand) != 0x00)
727 1 {
728 2 rdval = MI_INTERFACEERR;
729 2 }
730 1
731 1 WriteRawIO(RegPage,0x00); // configure to linear address mode
732 1
733 1 return rdval;
734 1 }
C51 COMPILER V8.00 MFRC500 04/23/2009 15:56:15 PAGE 13
735
736 /********************************
737 * SET DEFAULT COMM ATTRIB *
738 ********************************/
739 uchar M500PcdSetDefaultAttrib(void)
740 {
741 1 uchar status = MI_OK;
742 1 /*
743 1 WriteRawIO(RegTimerClock,0x07);
744 1 WriteRawIO(RegInterruptRq,0x7F);//clear all inter
745 1
746 1 SetBitMask(RegControl,0x04); //StopTimer
747 1 WriteRawIO(RegTxControl,0x5b);
748 1
749 1 //WriteRawRC(RegInterruptEn,0x7F);//disable all interrupts
750 1 //WriteRawRC(RegInterruptEn,0x88);
751 1 //WriteRawRC(RegChannelRedundancy,0x00); //no parity, no crc ; 03, en parity
752 1 //ClearBitMask(RegControl,0x08); // disable crypto 1 unit
753 1 //WriteRawRC(RegBitFraming,0x07); // set TxLastBits to 7
754 1
755 1 WriteRawIO(RegInterruptEn,0x7f);
756 1 //WriteRawRC(RegInterruptEn,0x88);
757 1
758 1 FlushFIFO();*/
759 1 return status;
760 1 }
761
762 /********************************
763 * mfrc500 request card *
764 * req_code: type of request *
765 * atq: answer to request *
766 ********************************/
767 uchar M500Request(uchar req_code, uchar *atq)
768 {
769 1
770 1 uchar idata status = MI_OK;
771 1
772 1 M500PcdSetDefaultAttrib();
773 1
774 1 // ClearBitMask(RegTxControl,0x03); // 050418
775 1 // delay(2); // same as upon
776 1
777 1 WriteIO(RegChannelRedundancy,0x03); // 03
778 1 ClearBitMask(RegControl,0x08);
779 1 WriteIO(RegBitFraming,0x07);
780 1
781 1 // M500PcdRfReset(3); ///////////// 050418
782 1
783 1 ResetInfo(&MInfo);
784 1 SndBuffer[0] = req_code;
785 1 MInfo.nBytesToSend = 1;
786 1 M500PcdSetTmo(3); // 2 050418 设置时间为6.0ms
787 1 status = M500PcdCmd(PCD_TRANSCEIVE, SndBuffer, RcvBuffer, &MInfo);
788 1
789 1
790 1 if (status)
791 1 {
792 2 *atq = 0;
793 2 }
794 1 else
795 1 {
796 2 if (MInfo.nBitsReceived != 16)
C51 COMPILER V8.00 MFRC500 04/23/2009 15:56:15 PAGE 14
797 2 {
798 3 *atq = 0;
799 3 status = MI_BITCOUNTERR;
800 3 }
801 2 else
802 2 {
803 3 status = MI_OK;
804 3 memcpy(atq, RcvBuffer, 2);
805 3 }
806 2 }
807 1 return status;
808 1 }
809
810 uchar M500Anticoll(uchar *Snr)
811 {
812 1
813 1 register uchar i;
814 1 uchar idata status = MI_OK;
815 1 uchar idata nbytes = 0;
816 1 uchar idata bcnt = 0;
817 1 uchar idata nbits = 0;
818 1 uchar idata complete = 0;
819 1 uchar idata byteOffset = 0;
820 1 uchar idata snr_crc;
821 1 uchar idata snr_check;
822 1 uchar idata dummyShift1;
823 1 uchar idata dummyShift2;
824 1
825 1 M500PcdSetDefaultAttrib();
826 1
827 1 M500PcdSetTmo(2); // 1 050418
828 1
829 1 WriteIO(RegDecoderControl,0x28);
830 1 ClearBitMask(RegControl,0x08);
831 1
832 1 complete = 0;
833 1 while (!complete && (status == MI_OK) )
834 1 {
835 2
836 2 ResetInfo(&MInfo);
837 2 WriteIO(RegChannelRedundancy,0x03);
838 2 nbits = bcnt % 8;
839 2 if (nbits)
840 2 {
841 3 WriteIO(RegBitFraming,nbits << 4 | nbits);
842 3 nbytes = bcnt / 8 + 1;
843 3 if (nbits == 7)
844 3 {
845 4 MInfo.cmd = PICC_ANTICOLL1;
846 4 WriteIO(RegBitFraming,nbits);
847 4 }
848 3 }
849 2 else
850 2 {
851 3 nbytes = bcnt / 8;
852 3 }
853 2
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