📄 mfrc500.lst
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280 2 break;
281 2
282 2 default:
283 2 status = MI_UNKNOWN_COMMAND;
284 2 break;
285 2 }
286 1
287 1 if (status == MI_OK)
288 1 {
289 2 irqEn |= 0x20;
290 2 waitFor |= 0x20;
291 2
292 2 for(i=0;i<253;i++)
293 2 {
294 3 _nop_();
295 3 }
296 2
297 2 WriteIO(RegInterruptEn,irqEn | 0x80); // enable interrupt
298 2
299 2 WriteIO(RegCommand,cmdcode); // send command
300 2 starttime = GetTickCount();
301 2
302 2 while (!((MpIsrInfo->irqSource & waitFor)
C51 COMPILER V8.00 MFRC500 04/23/2009 15:56:15 PAGE 6
303 2 || (GetTickCount() - starttime > 420))); // wait for cmd completion or timeout
304 2
305 2 //while(!MpIsrInfo->irqSource & waitFor);
306 2
307 2 // disableme(); // disable interrupt just when cmd complete, 050517
308 2
309 2 WriteIO(RegInterruptEn,0x7F); // disable all interrupts
310 2 WriteIO(RegInterruptRq,0x7F); // clear all interrupt requests
311 2 SetBitMask(RegControl,0x04); // stop timer now
312 2 WriteIO(RegCommand,PCD_IDLE); // reset command register
313 2
314 2 if (!(MpIsrInfo->irqSource & waitFor)) // reader has not terminated This logic has a problem a
-bout the timeout!!
315 2 { // timer 3 expired
316 3 status = MI_ACCESSTIMEOUT; // This code do not support the MiarePro. freqence timeout!!!
317 3 }
318 2 else
319 2 status = MpIsrInfo->status; // set status The real timeout occured ,then will the N
-O_TAGERR!
320 2
321 2 if (status == MI_OK) // no timeout error occured
322 2 {
323 3 if (tmpStatus = (ReadIO(RegErrorFlag) & 0x17/*0x1f*/)) // error occured
324 3 {
325 4 if (tmpStatus & 0x01) // collision detected
326 4 {
327 5 info->collPos = ReadIO(RegCollpos); // read collision position
328 5 status = MI_COLLERR;
329 5 }
330 4 else
331 4 {
332 5 info->collPos = 0;
333 5 if (tmpStatus & 0x02) // parity error
334 5 {
335 6 status = MI_PARITYERR;
336 6 }
337 5 }
338 4
339 4 if (tmpStatus & 0x04) // framing error
340 4 {
341 5 status = MI_FRAMINGERR;
342 5 }
343 4 if (tmpStatus & 0x10) // FIFO overflow
344 4 {
345 5 FlushFIFO();
346 5 status = MI_OVFLERR;
347 5 }
348 4 if (tmpStatus & 0x08) //CRC error
349 4 {
350 5 status = MI_CRCERR;
351 5 }
352 4 if (status == MI_OK)
353 4 status = MI_NY_IMPLEMENTED;
354 4 // key error occures always, because of
355 4 // missing crypto 1 keys loaded
356 4 }
357 3 // if the last command was TRANSCEIVE, the number of
358 3 // received bits must be calculated - even if an error occured
359 3 if (cmdcode == PCD_TRANSCEIVE || cmdcode == PCD_RECEIVE) ////////////////////
360 3 {
361 4 // number of bits in the last byte
362 4 lastBits = ReadIO(RegSecondaryStatus) & 0x07;
C51 COMPILER V8.00 MFRC500 04/23/2009 15:56:15 PAGE 7
363 4 if (lastBits)
364 4 info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
365 4 else
366 4 info->nBitsReceived += info->nBytesReceived * 8;
367 4 }
368 3 }
369 2 else
370 2 {
371 3 info->collPos = 0x00;
372 3 }
373 2 }
374 1 disableme();
375 1
376 1 MpIsrInfo = 0; // reset interface variables for ISR
377 1 MpIsrOut = 0;
378 1 MpIsrIn = 0;
379 1 return status;
380 1 }
381 #else
//////////////////////////////////////////////////////////////////////
// W R I T E A P C D C O M M A N D
///////////////////////////////////////////////////////////////////////
char M500PcdCmd(unsigned char cmd,
volatile unsigned char* send,
volatile unsigned char* rcv,
volatile MfCmdInfo *info)
{
char status = MI_OK;
char tmpStatus ;
unsigned char lastBits;
unsigned char irqEn = 0x00;
unsigned char waitFor = 0x00;
unsigned char timerCtl = 0x00;
WriteIO(RegInterruptEn,0x7F); // disable all interrupts
WriteIO(RegInterruptRq,0x7F); // reset interrupt requests
WriteIO(RegCommand,PCD_IDLE); // terminate probably running command
FlushFIFO(); // flush FIFO buffer
// save info structures to module pointers
MpIsrInfo = info;
MpIsrOut = send;
MpIsrIn = rcv;
info->irqSource = 0x0; // reset interrupt flags
enableme();
// depending on the command code, appropriate interrupts are enabled (irqEn)
// and the commit interrupt is choosen (waitFor).
switch(cmd)
{
case PCD_IDLE: // nothing else required
irqEn = 0x00;
waitFor = 0x00;
break;
case PCD_WRITEE2: // LoAlert and TxIRq
irqEn = 0x11;
waitFor = 0x10;
break;
C51 COMPILER V8.00 MFRC500 04/23/2009 15:56:15 PAGE 8
case PCD_READE2: // HiAlert, LoAlert and IdleIRq
irqEn = 0x07;
waitFor = 0x04;
break;
case PCD_LOADCONFIG: // IdleIRq and LoAlert
case PCD_LOADKEYE2: // IdleIRq and LoAlert
case PCD_AUTHENT1: // IdleIRq and LoAlert
irqEn = 0x05;
waitFor = 0x04;
break;
case PCD_CALCCRC: // LoAlert and TxIRq
irqEn = 0x11;
waitFor = 0x10;
break;
case PCD_AUTHENT2: // IdleIRq
irqEn = 0x04;
waitFor = 0x04;
break;
case PCD_RECEIVE: // HiAlert and IdleIRq
info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
irqEn = 0x06;
waitFor = 0x04;
break;
case PCD_LOADKEY: // IdleIRq
irqEn = 0x05;
waitFor = 0x04;
break;
case PCD_TRANSMIT: // LoAlert and IdleIRq
irqEn = 0x05;
waitFor = 0x04;
break;
case PCD_TRANSCEIVE: // TxIrq, RxIrq, IdleIRq and LoAlert
info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
irqEn = 0x3D;
waitFor = 0x04;
break;
default:
status = MI_UNKNOWN_COMMAND;
}
if (status == MI_OK)
{
// Initialize uC Timer for global Timeout management
irqEn |= 0x20; // always enable timout irq
waitFor |= 0x20; // always wait for timeout
WriteIO(RegInterruptEn,irqEn | 0x80); //necessary interrupts are enabled // count up from 1
WriteIO(RegCommand,cmd); //start command
starttime = GetTickCount();
// wait for commmand completion
// a command is completed, if the corresponding interrupt occurs
// or a timeout is signaled
while (!(MpIsrInfo->irqSource & waitFor
|| T3IR)); // wait for cmd completion or timeout
WriteIO(RegInterruptEn,0x7F); // disable all interrupts
WriteIO(RegInterruptRq,0x7F); // clear all interrupt requests
SetBitMask(RegControl,0x04); // stop timer now
GT_vStopTmr(TIMER_4);
GT_vStopTmr(TIMER_3);
C51 COMPILER V8.00 MFRC500 04/23/2009 15:56:15 PAGE 9
LED_OFF;
T3IR = 0;
WriteIO(RegCommand,PCD_IDLE); // reset command register
if (!(MpIsrInfo->irqSource & waitFor)) // reader has not terminated
{ // timer 3 expired
status = MI_ACCESSTIMEOUT;
}
else
status = MpIsrInfo->status; // set status
if (status == MI_OK) // no timeout error occured
{
if ((tmpStatus = (ReadIO(RegErrorFlag) & 0x17))) // error occured
{
if (tmpStatus & 0x01) // collision detected
{
info->collPos = ReadIO(RegCollPos); // read collision position
status = MI_COLLERR;
}
else
{
info->collPos = 0;
if (tmpStatus & 0x02) // parity error
{
status = MI_PARITYERR;
}
}
if (tmpStatus & 0x04) // framing error
{
status = MI_FRAMINGERR;
}
if (tmpStatus & 0x10) // FIFO overflow
{
FlushFIFO();
status = MI_OVFLERR;
}
if (tmpStatus & 0x08) // CRC error
{
status = MI_CRCERR;
}
if (status == MI_OK)
status = MI_NY_IMPLEMENTED;
// key error occures always, because of
// missing crypto 1 keys loaded
}
// if the last command was TRANSCEIVE, the number of
// received bits must be calculated - even if an error occured
if (cmd == PCD_TRANSCEIVE || cmd == PCD_RECEIVE)
{
// number of bits in the last byte
lastBits = ReadIO(RegSecondaryStatus) & 0x07;
if (lastBits)
info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
else
info->nBitsReceived += info->nBytesReceived * 8;
}
}
else
{
info->collPos = 0x00;
C51 COMPILER V8.00 MFRC500 04/23/2009 15:56:15 PAGE 10
}
}
READER_INT_DISABLE;
PcdIsrFct = EmptyPcdIsrFct; // reset the ISR-Function pointer to
// an empty function body
// do this before clearing the Mp XXXX variables
MpIsrInfo = 0; // reset interface variables for ISR
MpIsrOut = 0;
MpIsrIn = 0;
return status;
}
#endif
564
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