📄 mfrc500.c.bak
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}
#endif
///////////////////////////////////////////////////////////////////////////////
// Interrupt Handler RC500
///////////////////////////////////////////////////////////////////////////////
void RC500ISR (void) interrupt 0 using 1 //Ext0 interrupt
{
#if 0
static unsigned char idata irqBits;
static unsigned char idata irqMask;
static unsigned char idata nbytes;
static unsigned char idata cnt;
IE0 = 0; // Clear interrupt request flag
if (MpIsrInfo && MpIsrOut && MpIsrIn) // transfer pointers have to be set
// correctly
{
while( ReadIO(RegPrimaryStatus) & 0x08) // loop while IRQ pending
// Attention: IRQ bit is
// inverted when used with
// low activ IRQ
{
irqMask = ReadIO(RegInterruptEn); // read enabled interrupts
// read pending interrupts
irqBits = ReadIO(RegInterruptRq) & irqMask;
MpIsrInfo->irqSource |= irqBits; // save pending interrupts
//************ LoAlertIRQ ******************
if (irqBits & 0x01) // LoAlert
{
nbytes = MFIFOLength - ReadIO(RegFIFOLength);
// less bytes to send, than space in FIFO
if ((MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent) <= nbytes)
{
nbytes = MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent;
WriteIO(RegInterruptEn,0x01); // disable LoAlert IRQ
}
// write remaining data to the FIFO
for ( cnt = 0;cnt < nbytes;cnt++)
{
WriteIO(RegFIFOData,MpIsrOut[MpIsrInfo->nBytesSent]);
MpIsrInfo->nBytesSent++;
}
WriteIO(RegInterruptRq,0x01); // reset IRQ bit
}
//************* TxIRQ Handling **************
if (irqBits & 0x10) // TxIRQ
{
WriteIO(RegInterruptRq,0x10); // reset IRQ bit
WriteIO(RegInterruptEn,0x82); // enable HiAlert Irq for
// response
if (MpIsrInfo->cmd == PICC_ANTICOLL1) // if cmd is anticollision
{ // switch off parity generation
WriteIO(RegChannelRedundancy,0x02); // RXCRC and TXCRC disable, parity disable
}
}
//************* HiAlertIRQ or RxIRQ Handling ******************
if (irqBits & 0x0E) // HiAlert, Idle or RxIRQ
{
// read some bytes ( length of FIFO queue)
// into the receive buffer
nbytes = ReadIO(RegFIFOLength);
// read date from the FIFO and store them in the receive buffer
for ( cnt = 0; cnt < nbytes; cnt++)
{
MpIsrIn[MpIsrInfo->nBytesReceived] = ReadIO(RegFIFOData);
MpIsrInfo->nBytesReceived++;
}
WriteIO(RegInterruptRq,0x0A & irqBits);
// reset IRQ bit - idle irq will
// be deleted in a seperate section
}
//************** IdleIRQ Handling ***********
if (irqBits & 0x04) // Idle IRQ
{
WriteIO(RegInterruptEn,0x20); // disable Timer IRQ
WriteIO(RegInterruptRq,0x20); // disable Timer IRQ request
irqBits &= ~0x20; // clear Timer IRQ in local var
MpIsrInfo->irqSource &= ~0x20; // clear Timer IRQ in info var
// when idle received, then cancel
// timeout
WriteIO(RegInterruptRq,0x04); // reset IRQ bit
// status should still be MI_OK
// no error - only used for wake up
}
//************* TimerIRQ Handling ***********
if (irqBits & 0x20) // timer IRQ
{
WriteIO(RegInterruptRq,0x20); // reset IRQ bit
MpIsrInfo->status = MI_NOTAGERR; // timeout error
// otherwise ignore the interrupt
}
}
}
#else
static unsigned char idata irqBits;
static unsigned char idata irqMask;
static unsigned char idata oldPageSelect;
static unsigned char idata nbytes;
static unsigned char idata cnt;
if (MpIsrInfo && MpIsrOut && MpIsrIn) // transfer pointers have to be set
// correctly
{
oldPageSelect = ReadRawIO(RegPage); // save old page select
// Attention: ReadIO cannnot be
// used because of the internal
// write sequence to the page
// reg
WriteRawIO(RegPage,0x80); // select page 0 for ISR
while( (ReadRawIO(RegPrimaryStatus) & 0x08)) // loop while IRQ pending
{
irqMask = ReadRawIO(RegInterruptEn); // read enabled interrupts
// read pending interrupts
irqBits = ReadRawIO(RegInterruptRq) & irqMask;
MpIsrInfo->irqSource |= irqBits; // save pending interrupts
//************ LoAlertIRQ ******************
if (irqBits & 0x01) // LoAlert
{
nbytes = MFIFOLength - ReadRawIO(RegFIFOLength);
// less bytes to send, than space in FIFO
if ((MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent) <= nbytes)
{
nbytes = MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent;
WriteRawIO(RegInterruptEn,0x01); // disable LoAlert IRQ
}
// write remaining data to the FIFO
for ( cnt = 0;cnt < nbytes;cnt++)
{
WriteRawIO(RegFIFOData,MpIsrOut[MpIsrInfo->nBytesSent]);
MpIsrInfo->nBytesSent++;
}
WriteRawIO(RegInterruptRq,0x01); // reset IRQ bit
}
//************* TxIRQ Handling **************
if (irqBits & 0x10) // TxIRQ
{
WriteRawIO(RegInterruptRq,0x10); // reset IRQ bit
WriteRawIO(RegInterruptEn,0x82); // enable HiAlert Irq for
// response
if (MpIsrInfo->cmd == PICC_ANTICOLL1) // if cmd is anticollision
{ // switch off parity generation
WriteIO(RegChannelRedundancy,0x02); // RxCRC and TxCRC disable, parity disable
WriteRawIO(RegPage,0x00); // reset page address
}
}
//************* HiAlertIRQ or RxIRQ Handling ******************
if (irqBits & 0x0E) // HiAlert, Idle or RxIRQ
{
// read some bytes ( length of FIFO queue)
// into the receive buffer
nbytes = ReadRawIO(RegFIFOLength);
// read date from the FIFO and store them in the receive buffer
for ( cnt = 0; cnt < nbytes; cnt++)
{
MpIsrIn[MpIsrInfo->nBytesReceived] = ReadRawIO(RegFIFOData);
MpIsrInfo->nBytesReceived++;
}
WriteRawIO(RegInterruptRq,0x0A & irqBits);
// reset IRQ bit - idle irq will
// be deleted in a seperate section
}
//************** IdleIRQ Handling ***********
if (irqBits & 0x04) // Idle IRQ
{
WriteRawIO(RegInterruptEn,0x20); // disable Timer IRQ
WriteRawIO(RegInterruptRq,0x20); // disable Timer IRQ request
irqBits &= ~0x20; // clear Timer IRQ in local var
MpIsrInfo->irqSource &= ~0x20; // clear Timer IRQ in info var
// when idle received, then cancel
// timeout
WriteRawIO(RegInterruptRq,0x04); // reset IRQ bit
// status should still be MI_OK
// no error - only used for wake up
}
//************* TimerIRQ Handling ***********
if (irqBits & 0x20) // timer IRQ
{
WriteRawIO(RegInterruptRq,0x20); // reset IRQ bit
MpIsrInfo->status = MI_NOTAGERR; // timeout error
// otherwise ignore the interrupt
}
}
WriteRawIO(RegPage,oldPageSelect | 0x80);
}
#endif
}
/***************************************************************************************
****************************************************************************************
*
代码段说明: 以下代码专用于Mifare Pro卡片的操作函数. * *
*
代码核心函数: M500PiccExchangeBlock. *
*
功能说明: 数据块交换数据. *
*
*
****************************************************************************************
****************************************************************************************/
char M500PiccActivateIdle( unsigned char br,
unsigned char *atq,
unsigned char *sak,
unsigned char *uid,
unsigned char *uid_len);
/*
char M500PiccCascSelect(unsigned char select_code,
unsigned char *snr,
unsigned char *sak)
{
char status = MI_OK;
if ((status = M500PcdSetDefaultAttrib()) == MI_OK)
{
PcdSetTmo(106);
WriteIO(RegChannelRedundancy,0x0F); // RxCRC,TxCRC, Parity enable
ClearBitMask(RegControl,0x08); // disable crypto 1 unit
//************* Cmd Sequence **********************************
ResetInfo(&MInfo);
SndBuffer[0] = select_code;
SndBuffer[1] = 0x70; // number of bytes send
memcpy(SndBuffer + 2,snr,4);
SndBuffer[6] = SndBuffer[2]
^ SndBuffer[3]
^ SndBuffer[4]
^ SndBuffer[5];
MInfo.nBytesToSend = 7;
// MInfo.DisableDF = 1;
status = M500PcdCmd(PCD_TRANSCEIVE,
SndBuffer,
RcvBuffer,
&MInfo);
*sak = 0;
if (status == MI_OK) // no timeout occured
{
if (MInfo.nBitsReceived != 8) // last byte is not complete
{
status = MI_BITCOUNTERR;
}
else
{
memcpy(MLastSelectedSnr,snr,4);
}
}
// copy received data in any case - for debugging reasons
*sak = RcvBuffer[0];
}
return status;
} */
/*
char M500PiccCascAnticoll (unsigned char select_code,
unsigned char bcnt,
unsigned char *snr)
{
char status = MI_OK;
char snr_in[4]; // copy of the input parameter snr
char nbytes = 0; // how many bytes received
char nbits = 0; // how many bits received
char complete = 0; // complete snr recived
short i = 0;
char byteOffset = 0;
unsigned char snr_crc; // check byte calculation
unsigned char snr_check;
// unsigned char dummyShift1; // dummy byte for snr shift
// unsigned char dummyShift2; // dummy byte for snr shift
//************* Initialisierung ******************************
if ((status = M500PcdSetDefaultAttrib()) == MI_OK)
{
PcdSetTmo(106);
memcpy(snr_in,snr,4);
WriteIO(RegDecoderControl,0x28); // ZeroAfterColl aktivieren
ClearBitMask(RegControl,0x08); // disable crypto 1 unit
//************** Anticollision Loop ***************************
complete=0;
while (!complete && (status == MI_OK) )
{
// if there is a communication problem on the RF interface, bcnt
// could be larger than 32 - folowing loops will be defective.
if (bcnt > 32)
{
status = MI_WRONG_PARAMETER_VALUE;
continue;
}
ResetInfo(&MInfo);
MInfo.cmd = select_code; // pass command flag to ISR
// MInfo.DisableDF = 1;
WriteIO(RegChannelRedundancy,0x03); // RxCRC and TxCRC disable, parity enable
nbits = bcnt % 8; // remaining number of bits
if (nbits)
{
WriteIO(RegBitFraming,nbits << 4 | nbits); // TxLastBits/RxAlign auf nb_bi
nbytes = bcnt / 8 + 1;
// number of bytes known
// in order to solve an inconsistancy in the anticollision sequence
// (will be solved soon), the case of 7 bits has to be treated in a
// separate way
if (nbits == 7 )
{
// MInfo.RxAlignWA = 1;
MInfo.nBitsReceived = 7; // set flag for 7 bit anticoll, which is evaluated
// in the ISRnBitsReceived
WriteIO(RegBitFraming,nbits); // reset RxAlign to zero
}
}
else
{
nbytes = bcnt / 8;
}
SndBuffer[0] = select_code;
SndBuffer[1] = 0x20 + ((bcnt/8) << 4) + nbits; //number of bytes send
for (i = 0; i < nbytes; i++) // Sende Buffer beschreiben
{
SndBuffer[i + 2] = snr_in[i];
}
MInfo.nBytesToSend = 2 + nbytes;
status = M500PcdCmd(PCD_TRANSCEIVE,
SndBuffer,
RcvBuffer,
&MInfo);
// in order to solve an inconsistancy in the anticollision sequence
// (will be solved soon), the case of 7 bits has to be treated in a
// separate way
/* if (MInfo.RxAlignWA)
{
// reorder received bits
dummyShift1 = 0x00;
for (i = 0; i < MInfo.nBytesReceived; i++)
{
dummyShift2 = RcvBuffer[i];
RcvBuffer[i] = (dummyShift1 >> (i+1)) | (RcvBuffer[i] << (7-i));
dummyShift1 = dummyShift2;
}
MInfo.nBitsReceived -= MInfo.nBytesReceived; // subtract received parity bits
// recalculation of collision position
if ( MInfo.collPos ) MInfo.collPos += 7 - (MInfo.collPos + 6) / 9;
} */
/*
if ( status == MI_OK || status == MI_COLLERR) // no other occured
{
byteOffset = 0;
if ( nbits != 0 ) // last byte was not complete
{
snr_in[nbytes - 1] = snr_in[nbytes - 1] | RcvBuffer[0];
byteOffset = 1;
}
for ( i =0; i < (4 - nbytes); i++)
{
snr_in[nbytes + i] = RcvBuffer[i + byteOffset];
}
// R e s p o n s e P r o c e s s i n g
if ( MInfo.nBitsReceived != (40 - bcnt) ) // not 5 bytes answered
{
status = MI_BITCOUNTERR;
}
else
{
if (status != MI_COLLERR ) // no error and no collision
{
// SerCh check
snr_crc = snr_in[0] ^ snr_in[1] ^ snr_in[2] ^ snr_in[3];
snr_check = RcvBuffer[MInfo.nBytesReceived - 1];
if (snr_crc != snr_check)
{
status = MI_SERNRERR;
}
else
{
complete = 1;
}
}
else // collision occured
{
bcnt = bcnt + MInfo.collPos - nbits;
status = MI_OK;
}
}
}
}
}
// transfer snr_in to snr - even in case of an error - for
// debugging reasons
memcpy(snr,snr_in,4);
//----------------------Einstellungen aus Initialisierung ruecksetzen
ClearBitMask(RegDecoderControl,0x20); // ZeroAfterColl disable
return status;
} */
/*
char M500PiccActivateIdle(unsigned char br,
unsigned char *atq,
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