📄 m500auc.lst
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470 2 waitFor = 0x04;
471 2 break;
472 2 case PCD_CALCCRC: // LoAlert and TxIRq
473 2 irqEn = 0x11;
474 2 waitFor = 0x10;
475 2 break;
476 2 case PCD_AUTHENT2: // IdleIRq
477 2 irqEn = 0x04;
478 2 waitFor = 0x04;
479 2 break;
480 2 case PCD_RECEIVE: // HiAlert and IdleIRq
481 2 info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
482 2 irqEn = 0x06;
483 2 waitFor = 0x04;
484 2 break;
485 2 case PCD_LOADKEY: // IdleIRq
486 2 irqEn = 0x05;
487 2 waitFor = 0x04;
C51 COMPILER V7.02a M500AUC 07/24/2003 11:05:36 PAGE 9
488 2 break;
489 2 case PCD_TRANSMIT: // LoAlert and IdleIRq
490 2 irqEn = 0x05;
491 2 waitFor = 0x04;
492 2 break;
493 2 case PCD_TRANSCEIVE: // TxIrq, RxIrq, IdleIRq and LoAlert
494 2 info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
495 2 irqEn = 0x3D;
496 2 waitFor = 0x04;
497 2 break;
498 2 default:
499 2 status = MI_UNKNOWN_COMMAND;
500 2 }
501 1 if (status == MI_OK)
502 1 {
503 2 // Initialize uC Timer for global Timeout management
504 2 irqEn |= 0x20; // always enable timout irq
505 2 waitFor |= 0x20; // always wait for timeout
506 2
507 2 // start_timeout(4000); // initialise and start guard timer for reader
508 2 // 50us resolution, 200ms
509 2
510 2 WriteIO(RegInterruptEn,irqEn | 0x80); //necessary interrupts are enabled
511 2 WriteIO(RegCommand,cmd); //start command
512 2
513 2 // wait for commmand completion
514 2 // a command is completed, if the corresponding interrupt occurs
515 2 // or a timeout is signaled
516 2
517 2 while (!(MpIsrInfo->irqSource & waitFor
518 2 || T2IR)); // wait for cmd completion or timeout
519 2
520 2 WriteIO(RegInterruptEn,0x7F); // disable all interrupts
521 2 WriteIO(RegInterruptRq,0x7F); // clear all interrupt requests
522 2 SetBitMask(RegControl,0x04); // stop timer now
523 2
524 2 // stop_timeout(); // stop timeout for reader
525 2 WriteIO(RegCommand,PCD_IDLE); // reset command register
526 2
527 2
528 2 if (!(MpIsrInfo->irqSource & waitFor)) // reader has not terminated
529 2 { // timer 2 expired
530 3 status = MI_ACCESSTIMEOUT;
531 3 }
532 2 else
533 2 status = MpIsrInfo->status; // set status
534 2
535 2 if (status == MI_OK) // no timeout error occured
536 2 {
537 3 if (tmpStatus = (ReadIO(RegErrorFlag) & 0x17)) // error occured
538 3 {
539 4 if (tmpStatus & 0x01) // collision detected
540 4 {
541 5 info->collPos = ReadIO(RegCollpos); // read collision position
542 5 status = MI_COLLERR;
543 5 }
544 4 else
545 4 {
546 5 info->collPos = 0;
547 5 if (tmpStatus & 0x02) // parity error
548 5 {
549 6 status = MI_PARITYERR;
C51 COMPILER V7.02a M500AUC 07/24/2003 11:05:36 PAGE 10
550 6 }
551 5 }
552 4 if (tmpStatus & 0x04) // framing error
553 4 {
554 5 status = MI_FRAMINGERR;
555 5 }
556 4 if (tmpStatus & 0x10) // FIFO overflow
557 4 {
558 5 FlushFIFO();
559 5 status = MI_OVFLERR;
560 5 }
561 4 if (tmpStatus & 0x08) //CRC error
562 4 {
563 5 status = MI_CRCERR;
564 5 }
565 4 if (status == MI_OK)
566 4 status = MI_NY_IMPLEMENTED;
567 4 // key error occures always, because of
568 4 // missing crypto 1 keys loaded
569 4 }
570 3 // if the last command was TRANSCEIVE, the number of
571 3 // received bits must be calculated - even if an error occured
572 3 if (cmd == PCD_TRANSCEIVE)
573 3 {
574 4 // number of bits in the last byte
575 4 lastBits = ReadIO(RegSecondaryStatus) & 0x07;
576 4 if (lastBits)
577 4 info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
578 4 else
579 4 info->nBitsReceived += info->nBytesReceived * 8;
580 4 }
581 3 }
582 2 else
583 2 {
584 3 info->collPos = 0x00;
585 3 }
586 2 }
587 1 MpIsrInfo = 0; // reset interface variables for ISR
588 1 MpIsrOut = 0;
589 1 MpIsrIn = 0;
590 1 return status;
591 1 }
592
593 //////////////////////////////////////////////////////////////////////
594 // S E T A B I T M A S K
595 ///////////////////////////////////////////////////////////////////////
596 char SetBitMask(unsigned char reg,unsigned char mask) //
597 {
598 1 char idata tmp = 0x0;
599 1
600 1 tmp = ReadIO(reg);
601 1 WriteIO(reg,tmp | mask); // set bit mask
602 1 return 0x0;
603 1 }
604
605 //////////////////////////////////////////////////////////////////////
606 // C L E A R A B I T M A S K
607 ///////////////////////////////////////////////////////////////////////
608 char ClearBitMask(unsigned char reg,unsigned char mask) //
609 {
610 1 char idata tmp = 0x0;
611 1
C51 COMPILER V7.02a M500AUC 07/24/2003 11:05:36 PAGE 11
612 1 tmp = ReadIO(reg);
613 1 WriteIO(reg,tmp & ~mask); // clear bit mask
614 1 return 0x0;
615 1 }
616
617 ///////////////////////////////////////////////////////////////////////
618 // F L U S H F I F O
619 ///////////////////////////////////////////////////////////////////////
620 void FlushFIFO(void)
621 {
622 1 SetBitMask(RegControl,0x01);
623 1 }
624
625 ///////////////////////////////////////////////////////////////////////
626 // M I F A R E M O D U L E R E S E T
627 ///////////////////////////////////////////////////////////////////////
628 char M500PcdReset(void)
629 {
630 1 char idata status = MI_OK;
631 1
632 1 RC500RST = 0; // clear reset pin
633 1 // delay_1ms(25); // wait for 25ms
634 1 delay(25);
635 1 RC500RST = 1; // reset RC500
636 1 //delay_50us(50); // wait for 2.5ms
637 1 delay(3);
638 1 RC500RST = 0; // clear reset pin
639 1
640 1 //start_timeout(42000); // count down with a period of 50 us
641 1 // 42000 * 50 us = 2.1 s
642 1
643 1 // wait until reset command recognized
644 1 while (((/*ReadRawIO*/ReadIO(RegCommand) & 0x3F) != 0x3F) && !T2IR);
645 1 // while reset sequence in progress
646 1 while ((/*ReadRawIO*/ReadIO(RegCommand) & 0x3F) && !T2IR);
647 1
648 1 // stop_timeout(); // stop timeout counter
649 1
650 1 if (T2IR) // If reader timeout occurs
651 1 {
652 2 status = MI_RESETERR; // respose of reader IC is not correct
653 2 T2IR = 0;
654 2 }
655 1 else
656 1 {
657 2 /*WriteRawIO*/WriteIO(RegPage,0x80); // Dummy access in order to determine the bus
658 2 // configuration
659 2 // necessary read access
660 2 // after first write access, the returned value
661 2 // should be zero ==> interface recognized
662 2 if (ReadRawIO(RegCommand) != 0x00)
663 2 {
664 3 status = MI_INTERFACEERR;
665 3 }
666 2 WriteRawIO(RegPage,0x00); // configure to linear address mode
667 2
668 2 }
669 1 return status;
670 1 }
671
672 ///////////////////////////////////////////////////////////////////////
673 // M I F A R E M O D U L E C O N F I G U R A T I O N
C51 COMPILER V7.02a M500AUC 07/24/2003 11:05:36 PAGE 12
674 ///////////////////////////////////////////////////////////////////////
675 char M500PcdConfig(void)
676 {
677 1 char idata status;
678 1 char idata i;
679 1 char idata j;
680 1
681 1 if ((status = M500PcdReset()) == MI_OK)
682 1 {
683 2 // test clock Q calibration - value in the range of 0x46 expected
684 2 WriteIO(RegClockQControl,0x0);
685 2 WriteIO(RegClockQControl,0x40);
686 2 //delay_50us(2); // wait approximately 100 us - calibration in progress
687 2 SoftDelayCyl(100);
688 2 ClearBitMask(RegClockQControl,0x40); // clear bit ClkQCalib for
689 2 // further calibration
690 2
691 2 // The following values for RegBitPhase and
692 2 // RegRxThreshold represents an optimal
693 2 // value for our demo package. For user
694 2 // implementation some changes could be
695 2 // necessary
696 2 // initialize bit phase
697 2 WriteIO(RegBitPhase,0xAD);
698 2
699 2 // initialize minlevel
700 2 WriteIO(RegRxThreshold,0xFF);
701 2
702 2 // disable auto power down
703 2 WriteIO(RegRxControl2,0x01);
704 2
705 2 // Depending on the processing speed of the
706 2 // operation environment, the waterlevel
707 2 // can be adapted. (not very critical for
708 2 // mifare applications)
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