📄 m500auc.lst
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232 // FUNCTION: FlushFIFO
233 // IN: -
234 // OUT: -
235 // RETURN:
236 // COMMENT: All remaining date in the FIFO of the reader module is
237 // erased by this function. Before wrinting new data or
238 // starting a new command, all remaining data from former
239 // commands should be deleted. Please note, that in
240 // normal operation, never data should be left, that means
C51 COMPILER V7.02a M500AUC 07/24/2003 11:05:36 PAGE 5
241 // that a call to this function should not be necessary.
242 //
243 void FlushFIFO(void);
244
245 // _____________________________________________________________________________
246 //
247 // FUNCTION: M500PiccAuthState
248 // IN: auth_mode
249 // snr
250 // sector
251 // OUT: -
252 // RETURN:
253 // COMMENT:
254 //
255 char M500PiccAuthState(unsigned char auth_mode,// PICC_AUTHENT1A, PICC_AUTHENT1B
256 unsigned char *snr, // 4 byte serial number
257 unsigned char sector); // 0 <= sector <= 15
258 // sector address for authentication
259
260 //////////////////////////////////////////////////////////////////////
261 // E X C H A N G E B Y T E S T R E A M
262 ///////////////////////////////////////////////////////////////////////
263 char ExchangeByteStream(unsigned char Cmd,
264 unsigned char *send_data,
265 unsigned char send_bytelen,
266 unsigned char *rec_data,
267 unsigned char *rec_bytelen);
268
269 //COMMENT: Initialize MCU'S I/O pins for RC500
270 //
271 void RC500IOInit()
272 {
273 1 // OpenIO();
274 1 IT0 = 1; // Config ext0 as edge trigger for RC500
275 1 EX0 = 1; // Enable ext0 interrupt for RC500
276 1
277 1 EA = 1;//TRUE; // Enable all interrupts
278 1
279 1 }
280
281
282 ///////////////////////////////////////////////////////////////////////////////
283 // Interrupt Handler RC500
284 ///////////////////////////////////////////////////////////////////////////////
285 void RC500ISR (void) interrupt 0 using 1 //Ext0 interrupt
286 {
287 1 static unsigned char idata irqBits;
288 1 static unsigned char idata irqMask;
289 1 static unsigned char idata nbytes;
290 1 static unsigned char idata cnt;
291 1
292 1 IE0 = 0; // Clear interrupt request flag
293 1
294 1 if (MpIsrInfo && MpIsrOut && MpIsrIn) // transfer pointers have to be set
295 1 // correctly
296 1 {
297 2 while( /*ReadRawIO*/ReadIO(RegPrimaryStatus) & 0x08) // loop while IRQ pending
298 2 // Attention: IRQ bit is
299 2 // inverted when used with
300 2 // low activ IRQ
301 2 {
302 3 irqMask = /*ReadRawIO*/ReadIO(RegInterruptEn); // read enabled interrupts
C51 COMPILER V7.02a M500AUC 07/24/2003 11:05:36 PAGE 6
303 3 // read pending interrupts
304 3 irqBits = /*ReadRawIO*/ReadIO(RegInterruptRq) & irqMask;
305 3 MpIsrInfo->irqSource |= irqBits; // save pending interrupts
306 3 //************ LoAlertIRQ ******************
307 3 if (irqBits & 0x01) // LoAlert
308 3 {
309 4 nbytes = MFIFOLength - /*ReadRawIO*/ReadIO(RegFIFOLength);
310 4 // less bytes to send, than space in FIFO
311 4 if ((MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent) <= nbytes)
312 4 {
313 5 nbytes = MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent;
314 5 /*WriteRawIO*/WriteIO(RegInterruptEn,0x01); // disable LoAlert IRQ
315 5 }
316 4 // write remaining data to the FIFO
317 4 for ( cnt = 0;cnt < nbytes;cnt++)
318 4 {
319 5 /*WriteRawIO*/WriteIO(RegFIFOData,MpIsrOut[MpIsrInfo->nBytesSent]);
320 5 MpIsrInfo->nBytesSent++;
321 5 }
322 4 /*WriteRawIO*/WriteIO(RegInterruptRq,0x01); // reset IRQ bit
323 4 }
324 3
325 3 //************* TxIRQ Handling **************
326 3 if (irqBits & 0x10) // TxIRQ
327 3 {
328 4 /*WriteRawIO*/WriteIO(RegInterruptRq,0x10); // reset IRQ bit
329 4 /*WriteRawIO*/WriteIO(RegInterruptEn,0x82); // enable HiAlert Irq for
330 4 // response
331 4 if (MpIsrInfo->cmd == PICC_ANTICOLL1) // if cmd is anticollision
332 4 { // switch off parity generation
333 5 /*WriteRawIO*/WriteIO(RegChannelRedundancy,0x02); // RXCRC and TXCRC disable, parity disabl
-e
334 5 }
335 4 }
336 3
337 3 //************* HiAlertIRQ or RxIRQ Handling ******************
338 3 if (irqBits & 0x0E) // HiAlert, Idle or RxIRQ
339 3 {
340 4 // read some bytes ( length of FIFO queue)
341 4 // into the receive buffer
342 4 nbytes = /*ReadRawIO*/ReadIO(RegFIFOLength);
343 4 // read date from the FIFO and store them in the receive buffer
344 4 for ( cnt = 0; cnt < nbytes; cnt++)
345 4 {
346 5 MpIsrIn[MpIsrInfo->nBytesReceived] = /*ReadRawIO*/ReadIO(RegFIFOData);
347 5 MpIsrInfo->nBytesReceived++;
348 5 }
349 4 /*WriteRawIO*/WriteIO(RegInterruptRq,0x0A & irqBits);
350 4 // reset IRQ bit - idle irq will
351 4 // be deleted in a seperate section
352 4 }
353 3
354 3 //************** IdleIRQ Handling ***********
355 3 if (irqBits & 0x04) // Idle IRQ
356 3 {
357 4 /*WriteRawIO*/WriteIO(RegInterruptEn,0x20); // disable Timer IRQ
358 4 /*WriteRawIO*/WriteIO(RegInterruptRq,0x20); // disable Timer IRQ request
359 4 irqBits &= ~0x20; // clear Timer IRQ in local var
360 4 MpIsrInfo->irqSource &= ~0x20; // clear Timer IRQ in info var
361 4 // when idle received, then cancel
362 4 // timeout
363 4 /*WriteRawIO*/WriteIO(RegInterruptRq,0x04); // reset IRQ bit
C51 COMPILER V7.02a M500AUC 07/24/2003 11:05:36 PAGE 7
364 4 // status should still be MI_OK
365 4 // no error - only used for wake up
366 4 }
367 3
368 3 //************* TimerIRQ Handling ***********
369 3 if (irqBits & 0x20) // timer IRQ
370 3 {
371 4 /*WriteRawIO*/WriteIO(RegInterruptRq,0x20); // reset IRQ bit
372 4 MpIsrInfo->status = MI_NOTAGERR; // timeout error
373 4 // otherwise ignore the interrupt
374 4 }
375 3
376 3 }
377 2 }
378 1 }
379
380 ///////////////////////////////////////////////////////////////////////
381 // S e t T i m e o u t L E N G T H
382 ///////////////////////////////////////////////////////////////////////
383 void M500PcdSetTmo(unsigned char tmoLength)
384 {
385 1 switch(tmoLength)
386 1 { // timer clock frequency 13,56 MHz
387 2 case 1: // short timeout (1,0 ms)
388 2 WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
389 2 WriteIO(RegTimerReload,0x6a);// TReloadVal = 'h6a =106(dec)
390 2 break;
391 2 case 2: // medium timeout (1,5 ms)
392 2 WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
393 2 WriteIO(RegTimerReload,0xa0);// TReloadVal = 'ha0 =160(dec)
394 2 break;
395 2 case 3: // medium timeout (6 ms)
396 2 WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
397 2 WriteIO(RegTimerReload,0xa0);// TReloadVal = 'ha0 =160(dec)
398 2 break;
399 2 case 4: // long timeout (9.6 ms)
400 2 WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
401 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
402 2 break;
403 2 case 5: // long timeout (38.5 ms)
404 2 WriteIO(RegTimerClock,0x0b); // TAutoRestart=0,TPrescale=16*128
405 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
406 2 break;
407 2 case 6: // long timeout (154 ms)
408 2 WriteIO(RegTimerClock,0x0d); // TAutoRestart=0,TPrescale=64*128
409 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
410 2 break;
411 2 case 7: // long timeout (616.2 ms)
412 2 WriteIO(RegTimerClock,0x0f); // TAutoRestart=0,TPrescale=256*128
413 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
414 2 break;
415 2 default: //
416 2 WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
417 2 WriteIO(RegTimerReload,tmoLength);// TReloadVal = 'h6a =tmoLength(dec)
418 2 break;
419 2 }
420 1 }
421
422 //////////////////////////////////////////////////////////////////////
423 // W R I T E A P C D C O M M A N D
424 ///////////////////////////////////////////////////////////////////////
425 char M500PcdCmd(unsigned char cmd,
C51 COMPILER V7.02a M500AUC 07/24/2003 11:05:36 PAGE 8
426 volatile unsigned char* send,
427 volatile unsigned char* rcv,
428 volatile MfCmdInfo *info)
429 {
430 1 char idata status = MI_OK;
431 1 char idata tmpStatus ;
432 1 unsigned char idata lastBits;
433 1
434 1 unsigned char idata irqEn = 0x00;
435 1 unsigned char idata waitFor = 0x00;
436 1 unsigned char idata timerCtl = 0x00;
437 1
438 1 WriteIO(RegInterruptEn,0x7F); // disable all interrupts
439 1 WriteIO(RegInterruptRq,0x7F); // reset interrupt requests
440 1 WriteIO(RegCommand,PCD_IDLE); // terminate probably running command
441 1
442 1 FlushFIFO(); // flush FIFO buffer
443 1
444 1 // save info structures to module pointers
445 1 MpIsrInfo = info;
446 1 MpIsrOut = send;
447 1 MpIsrIn = rcv;
448 1
449 1 info->irqSource = 0x0; // reset interrupt flags
450 1 // depending on the command code, appropriate interrupts are enabled (irqEn)
451 1 // and the commit interrupt is choosen (waitFor).
452 1 switch(cmd)
453 1 {
454 2 case PCD_IDLE: // nothing else required
455 2 irqEn = 0x00;
456 2 waitFor = 0x00;
457 2 break;
458 2 case PCD_WRITEE2: // LoAlert and TxIRq
459 2 irqEn = 0x11;
460 2 waitFor = 0x10;
461 2 break;
462 2 case PCD_READE2: // HiAlert, LoAlert and IdleIRq
463 2 irqEn = 0x07;
464 2 waitFor = 0x04;
465 2 break;
466 2 case PCD_LOADCONFIG: // IdleIRq
467 2 case PCD_LOADKEYE2: // IdleIRq
468 2 case PCD_AUTHENT1: // IdleIRq
469 2 irqEn = 0x05;
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