📄 rx2flash.src
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; .\out_sst89e564\rx2flash.SRC generated from: source\rx2flash.c
; COMPILER INVOKED BY:
; C:\Keil\C51\BIN\C51.EXE source\rx2flash.c LARGE BROWSE ORDER NOAREGS DEBUG OBJECTEXTEND PRINT(.\rx2flash.lst) SRC(.\out_sst89e564\rx2flash.SRC)
$NOMOD51
NAME RX2FLASH
FSB DATA 0B6H
WDTC DATA 0C0H
WDTD DATA 085H
AUXR DATA 08EH
CKCON DATA 08FH
AUXR1 DATA 0A2H
WDTRST DATA 0A6H
WDTPRG DATA 0A7H
SADDR DATA 0A9H
IPH DATA 0B7H
IPH0 DATA 0B7H
SADEN DATA 0B9H
IPL DATA 0B8H
IPL0 DATA 0B8H
EECON DATA 0D2H
EETIM DATA 0D3H
FCON DATA 0D1H
CCON DATA 0D8H
CMOD DATA 0D9H
CCAPM0 DATA 0DAH
CCAPM1 DATA 0DBH
CCAPM2 DATA 0DCH
CCAPM3 DATA 0DDH
CCAPM4 DATA 0DEH
P5 DATA 0E8H
CL DATA 0E9H
CCAP0L DATA 0EAH
CCAP1L DATA 0EBH
CCAP2L DATA 0ECH
CCAP3L DATA 0EDH
CCAP4L DATA 0EEH
CH DATA 0F9H
CCAP0H DATA 0FAH
CCAP1H DATA 0FBH
CCAP2H DATA 0FCH
CCAP3H DATA 0FDH
CCAP4H DATA 0FEH
P0 DATA 080H
SP DATA 081H
DPL DATA 082H
DPH DATA 083H
PCON DATA 087H
TCON DATA 088H
TMOD DATA 089H
TL0 DATA 08AH
TL1 DATA 08BH
TH0 DATA 08CH
TH1 DATA 08DH
P1 DATA 090H
SCON DATA 098H
SBUF DATA 099H
P2 DATA 0A0H
IE DATA 0A8H
P3 DATA 0B0H
IP DATA 0B8H
T2CON DATA 0C8H
T2MOD DATA 0C9H
RCAP2L DATA 0CAH
RCAP2H DATA 0CBH
TL2 DATA 0CCH
TH2 DATA 0CDH
PSW DATA 0D0H
ACC DATA 0E0H
B DATA 0F0H
P0_0 BIT 080H.0
P0_1 BIT 080H.1
P0_2 BIT 080H.2
P0_3 BIT 080H.3
P0_4 BIT 080H.4
P0_5 BIT 080H.5
P0_6 BIT 080H.6
P0_7 BIT 080H.7
IT0 BIT 088H.0
IE0 BIT 088H.1
IT1 BIT 088H.2
IE1 BIT 088H.3
TR0 BIT 088H.4
TF0 BIT 088H.5
TR1 BIT 088H.6
TF1 BIT 088H.7
P1_0 BIT 090H.0
P1_1 BIT 090H.1
P1_2 BIT 090H.2
P1_3 BIT 090H.3
P1_4 BIT 090H.4
P1_5 BIT 090H.5
P1_6 BIT 090H.6
P1_7 BIT 090H.7
T2 BIT 090H.0
T2EX BIT 090H.1
RI BIT 098H.0
TI BIT 098H.1
RB8 BIT 098H.2
TB8 BIT 098H.3
REN BIT 098H.4
SM2 BIT 098H.5
SM1 BIT 098H.6
SM0 BIT 098H.7
P2_0 BIT 0A0H.0
P2_1 BIT 0A0H.1
P2_2 BIT 0A0H.2
P2_3 BIT 0A0H.3
P2_4 BIT 0A0H.4
P2_5 BIT 0A0H.5
P2_6 BIT 0A0H.6
P2_7 BIT 0A0H.7
EX0 BIT 0A8H.0
ET0 BIT 0A8H.1
EX1 BIT 0A8H.2
ET1 BIT 0A8H.3
ES BIT 0A8H.4
ET2 BIT 0A8H.5
EA BIT 0A8H.7
P3_0 BIT 0B0H.0
P3_1 BIT 0B0H.1
P3_2 BIT 0B0H.2
P3_3 BIT 0B0H.3
P3_4 BIT 0B0H.4
P3_5 BIT 0B0H.5
P3_6 BIT 0B0H.6
P3_7 BIT 0B0H.7
RXD BIT 0B0H.0
TXD BIT 0B0H.1
INT0 BIT 0B0H.2
INT1 BIT 0B0H.3
T0 BIT 0B0H.4
T1 BIT 0B0H.5
WR BIT 0B0H.6
RD BIT 0B0H.7
PX0 BIT 0B8H.0
PT0 BIT 0B8H.1
PX1 BIT 0B8H.2
PT1 BIT 0B8H.3
PS BIT 0B8H.4
PT2 BIT 0B8H.5
CP_RL2 BIT 0C8H.0
C_T2 BIT 0C8H.1
TR2 BIT 0C8H.2
EXEN2 BIT 0C8H.3
TCLK BIT 0C8H.4
RCLK BIT 0C8H.5
EXF2 BIT 0C8H.6
TF2 BIT 0C8H.7
P BIT 0D0H.0
FL BIT 0D0H.1
OV BIT 0D0H.2
RS0 BIT 0D0H.3
RS1 BIT 0D0H.4
F0 BIT 0D0H.5
AC BIT 0D0H.6
CY BIT 0D0H.7
SFCF DATA 0B1H
SFCM DATA 0B2H
SFAL DATA 0B3H
SFAH DATA 0B4H
SFDT DATA 0B5H
SFST DATA 0B6H
?PR?ready?RX2FLASH SEGMENT CODE
?XD?ready?RX2FLASH SEGMENT XDATA OVERLAYABLE
?PR?_FlashWrByte?RX2FLASH SEGMENT CODE
?PR?_FlashErSector?RX2FLASH SEGMENT CODE
?PR?_FlashRdByte?RX2FLASH SEGMENT CODE
?C_INITSEG SEGMENT CODE
?XD?RX2FLASH SEGMENT XDATA
EXTRN CODE (GetTickCount)
EXTRN CODE (?C?LSTKXDATA)
EXTRN CODE (?C?ULCMP)
PUBLIC SECT_SIZE
PUBLIC BLK1_DST_ADDR
PUBLIC _FlashRdByte
PUBLIC _FlashErSector
PUBLIC _FlashWrByte
PUBLIC ready
RSEG ?XD?ready?RX2FLASH
?ready?BYTE:
TimeOut?040: DS 4
RSEG ?XD?RX2FLASH
BLK1_DST_ADDR: DS 2
SECT_SIZE: DS 1
RSEG ?C_INITSEG
DB 042H
DW BLK1_DST_ADDR
DW 01000H
DB 041H
DW SECT_SIZE
DB 080H
; /* rx2flash.c */
;
; //#include<reg51rd2.h>
; #include"types.h"
; #include"c51rx2.h"
; #include"reg52.h"
; #include"stimer.h"
;
; #ifdef WATCHDOG
; #define CLRWDT
; #endif
;
; #define _pusha() ;
; #define _popa() ;
;
; #ifndef _pusha
; void _pusha(void);
; void _popa(void);
; #endif
;
; /********************************************
; * FlashFlex51 MCU SFR Memory Addresses
; *********************************************/
; sfr SFCF = 0xB1; /*SuperFlash Configuration*/
; sfr SFCM = 0xB2; /*SuperFlash Command*/
; sfr SFAL = 0xB3; /*SuperFlash Address Low*/
; sfr SFAH = 0xB4; /*SuperFlash Address High*/
; sfr SFDT = 0xB5; /*SuperFlash Data*/
; sfr SFST = 0xB6; /*SuperFlash Status*/
; /********************************************
; * FlashFlex51 MCU IAP Commands
; *********************************************/
; #define SFCM_SE 0x0B; /*Sector-Erase IAP cmd*/
; #define SFCM_VB 0x0C; /*Byte-Verify IAP cmd*/
; #define SFCM_PB 0x0E; /*Byte-Program IAP cmd*/
; /********************************************
; * Global Variable Definition
; *********************************************/
; const unsigned short int BLK1_DST_ADDR = 0x1000;
; /*SST89x564RD destination address (in the other on-chip flash memory block)
; where data will be written to, which is above BSL code space.*/
;
; const unsigned char SECT_SIZE = 0x80; /*number of bytes in a sector*/
;
; // test if operation is ready
; bool ready()
RSEG ?PR?ready?RX2FLASH
ready:
USING 0
; SOURCE LINE # 46
; {
; SOURCE LINE # 47
; unsigned long int TimeOut = 0;
; SOURCE LINE # 48
MOV DPTR,#TimeOut?040
LCALL ?C?LSTKXDATA
DB 00H
DB 00H
DB 00H
DB 00H
?C0001:
;
; while (TimeOut < 100000)
; SOURCE LINE # 50
MOV R7,#0A0H
MOV R6,#086H
MOV R5,#01H
MOV R4,#00H
MOV DPTR,#TimeOut?040
MOVX A,@DPTR
MOV R0,A
INC DPTR
MOVX A,@DPTR
MOV R1,A
INC DPTR
MOVX A,@DPTR
MOV R2,A
INC DPTR
MOVX A,@DPTR
MOV R3,A
CLR C
LCALL ?C?ULCMP
JNC ?C0002
; {
; SOURCE LINE # 51
; if ((SFST&4) == 0) /* Check if IAP is done */
; SOURCE LINE # 52
MOV A,SFST
JB ACC.2,?C0003
; { /* IAP is done */
; SOURCE LINE # 53
; SFCF = SFCF & 0xBF; /* turn off IAP*/
; SOURCE LINE # 54
ANL SFCF,#0BFH
; SFDT = 0; /* any value other than 0x55 */
; SOURCE LINE # 55
CLR A
MOV SFDT,A
; return true; /* IAP operation is completed*/
; SOURCE LINE # 56
RET
; }
; SOURCE LINE # 57
?C0003:
; GetTickCount();
; SOURCE LINE # 58
LCALL GetTickCount
; }
; SOURCE LINE # 59
SJMP ?C0001
?C0002:
; SFCF = SFCF & 0xBF; /*turn off IAP*/
; SOURCE LINE # 60
ANL SFCF,#0BFH
; SFDT = 0; /*any value other than 0x55*/
; SOURCE LINE # 61
CLR A
MOV SFDT,A
; return false; /*IAP operation is NOT completed before time out*/
; SOURCE LINE # 62
CLR C
; }
; SOURCE LINE # 63
?C0004:
RET
; END OF ready
;
; // write a byte to flash
; bool FlashWrByte(uint addr, uchar ch)
RSEG ?PR?_FlashWrByte?RX2FLASH
_FlashWrByte:
USING 0
; SOURCE LINE # 66
;---- Variable 'addr?141' assigned to Register 'R2/R3' ----
XCH A,R3
MOV A,R7
XCH A,R3
XCH A,R2
MOV A,R6
XCH A,R2
;---- Variable 'ch?142' assigned to Register 'R5' ----
; {
; SOURCE LINE # 67
; disable();
; SOURCE LINE # 68
CLR EA
; SFCF = SFCF | 0x40; /*enable IAP */
; SOURCE LINE # 69
ORL SFCF,#040H
; SFAH = addr>>8; /*load high order address byte*/
; SOURCE LINE # 70
MOV A,R2
MOV SFAH,A
; SFAL = addr & 0xff; /*load low order address byte */
; SOURCE LINE # 71
MOV A,R3
MOV SFAL,A
; SFDT = ch; /*load data to be programmed */
; SOURCE LINE # 72
XCH A,R7
MOV A,R5
XCH A,R7
MOV SFDT,R7
; SFCM = SFCM_PB; /*issue byte program command */
; SOURCE LINE # 73
MOV SFCM,#0EH
;
; if(!ready())
; SOURCE LINE # 75
LCALL ready
JC ?C0005
; {
; SOURCE LINE # 76
; enable();
; SOURCE LINE # 77
SETB EA
; return false;
; SOURCE LINE # 78
RET
; }
; SOURCE LINE # 79
?C0005:
;
; enable();
; SOURCE LINE # 81
SETB EA
; return true;
; SOURCE LINE # 82
SETB C
; }
; SOURCE LINE # 83
?C0006:
RET
; END OF _FlashWrByte
;
; // erase sector
; // addr: 00h, 80h
; bool FlashErSector(uint addr)
RSEG ?PR?_FlashErSector?RX2FLASH
_FlashErSector:
USING 0
; SOURCE LINE # 87
;---- Variable 'addr?243' assigned to Register 'R4/R5' ----
XCH A,R5
MOV A,R7
XCH A,R5
XCH A,R4
MOV A,R6
XCH A,R4
; {
; SOURCE LINE # 88
; disable();
; SOURCE LINE # 89
CLR EA
; SFCF = SFCF | 0x40; /*enable IAP */
; SOURCE LINE # 90
ORL SFCF,#040H
; SFAH = addr>>8; /*load high order address byte*/
; SOURCE LINE # 91
MOV A,R4
MOV SFAH,A
; SFAL = addr & 0xff; /*load low order address byte */
; SOURCE LINE # 92
MOV A,R5
MOV SFAL,A
; SFCM = SFCM_SE; /*issue sector erase command */
; SOURCE LINE # 93
MOV SFCM,#0BH
;
; if(!ready())
; SOURCE LINE # 95
LCALL ready
JC ?C0007
; {
; SOURCE LINE # 96
; enable();
; SOURCE LINE # 97
SETB EA
; return false;
; SOURCE LINE # 98
RET
; }
; SOURCE LINE # 99
?C0007:
;
; enable();
; SOURCE LINE # 101
SETB EA
; return true;
; SOURCE LINE # 102
SETB C
; }
; SOURCE LINE # 103
?C0008:
RET
; END OF _FlashErSector
;
; // read device data
; uchar FlashRdByte(uint addr)
RSEG ?PR?_FlashRdByte?RX2FLASH
_FlashRdByte:
USING 0
; SOURCE LINE # 106
;---- Variable 'addr?344' assigned to Register 'R4/R5' ----
XCH A,R5
MOV A,R7
XCH A,R5
XCH A,R4
MOV A,R6
XCH A,R4
; {
; SOURCE LINE # 107
; unsigned char readByte;
; disable();
; SOURCE LINE # 109
CLR EA
; SFCF = SFCF | 0x40; /*enable IAP */
; SOURCE LINE # 110
ORL SFCF,#040H
; SFAH = addr>>8; /*load high order address byte*/
; SOURCE LINE # 111
MOV A,R4
MOV SFAH,A
; SFAL = addr & 0xff; /*load low order address byte */
; SOURCE LINE # 112
MOV A,R5
MOV SFAL,A
; SFCM = SFCM_VB; /*issue byte verify command */
; SOURCE LINE # 113
MOV SFCM,#0CH
; readByte = SFDT;
; SOURCE LINE # 114
;---- Variable 'readByte?345' assigned to Register 'R7' ----
MOV R7,SFDT
; SFCF = SFCF & 0xBF; /*turn off IAP*/
; SOURCE LINE # 115
ANL SFCF,#0BFH
; SFDT = 0;
; SOURCE LINE # 116
CLR A
MOV SFDT,A
; enable();
; SOURCE LINE # 117
SETB EA
; return readByte;
; SOURCE LINE # 118
; }
; SOURCE LINE # 119
?C0009:
RET
; END OF _FlashRdByte
END
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