📄 mfrc500.src
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; WriteIO(RegRxControl1, RxGain);//73:42db, 72:38, 71:30, 70:27
; SOURCE LINE # 489
MOV R7,#019H
LCALL _WriteIO
; M500PcdRfReset(5);
; SOURCE LINE # 490
MOV R7,#05H
LJMP _M500PcdRfReset
; END OF _M500SetRcvGain
; }
;
; /********************************
; * init mfrc500 *
; ********************************/
; uchar M500PcdInit(void)
RSEG ?PR?M500PcdInit?MFRC500
M500PcdInit:
USING 0
; SOURCE LINE # 496
; {
; SOURCE LINE # 497
; uchar miret = MI_OK;
; SOURCE LINE # 498
CLR A
MOV DPTR,#miret?759
MOVX @DPTR,A
;
; IT0 = 1; // edge
; SOURCE LINE # 500
SETB IT0
;
; SetIntPri(IE0_VECTOR, 2);
; SOURCE LINE # 502
MOV R5,#02H
MOV R7,A
LCALL _SetIntPri
;
; miret = M500PcdReset();
; SOURCE LINE # 504
LCALL M500PcdReset
MOV DPTR,#miret?759
MOV A,R7
MOVX @DPTR,A
; #ifdef FORCE_RESET
; if(miret != MI_OK)
; return miret;
; #endif
;
; WriteIO(RegClockQControl,0x00);
; SOURCE LINE # 510
CLR A
MOV R5,A
MOV R7,#01FH
LCALL _WriteIO
; WriteIO(RegClockQControl,0x40);
; SOURCE LINE # 511
MOV R5,#040H
MOV R7,#01FH
LCALL _WriteIO
; SoftDelayCyl(100);
; SOURCE LINE # 512
MOV R7,#064H
LCALL _SoftDelayCyl
; ClearBitMask(RegClockQControl,0x40); ////
; SOURCE LINE # 513
MOV R5,#040H
MOV R7,#01FH
LCALL _ClearBitMask
; // WriteIO(RegTxControl, 0x5b);//////////////////////////////////
;
; // The following values for RegBitPhase and
; // RegRxThreshold represents an optimal
; // value for our demo package. For user
; // implementation some changes could be
; // necessary
; // initialize bit phase
; WriteIO(RegBitPhase,0xAD);
; SOURCE LINE # 522
MOV R5,#0ADH
MOV R7,#01BH
LCALL _WriteIO
;
; // initialize minlevel
; WriteIO(RegRxThreshold,0xFF);
; SOURCE LINE # 525
MOV R5,#0FFH
MOV R7,#01CH
LCALL _WriteIO
;
; // disable auto power down
; //WriteIO(RegRxControl2,0x01);
; WriteIO(RegRxControl2,0x01);//C1 for Power saving, 01 for disable auto power down
; SOURCE LINE # 529
MOV R5,#01H
MOV R7,#01EH
LCALL _WriteIO
; //WriteIO(RegDecoderControl,0x28);/////////////////////////////////////////////
; WriteIO(RegRxControl1,RxGain);//73:42db, 72:38, 71:30, 70:27///////////////////
; SOURCE LINE # 531
MOV DPTR,#RxGain
MOVX A,@DPTR
MOV R5,A
MOV R7,#019H
LCALL _WriteIO
;
;
; // Depending on the processing speed of the
; // operation environment, the waterlevel
; // can be adapted. (not very critical for
; // mifare applications)
; // initialize waterlevel to value 4
; WriteIO(RegFIFOLevel,0x1a); // 4 // 1a
; SOURCE LINE # 539
MOV R5,#01AH
MOV R7,#029H
LCALL _WriteIO
;
; //Timer configuration
; WriteIO(RegTimerControl,0x02); // TStopRxEnd=0,TStopRxBeg=0, 2
; SOURCE LINE # 542
MOV R5,#02H
MOV R7,#02BH
LCALL _WriteIO
; // TStartTxEnd=1,TStartTxBeg=0
; // timer must be stopped manually
;
; WriteIO(RegIRqPinConfig,0x03); // interrupt active low enable
; SOURCE LINE # 546
MOV R5,#03H
MOV R7,#02DH
LCALL _WriteIO
;
;
; M500PcdRfReset(5); // Rf - reset and enable output driver //1-2
; SOURCE LINE # 549
MOV R7,#05H
LCALL _M500PcdRfReset
;
; return miret;
; SOURCE LINE # 551
MOV DPTR,#miret?759
MOVX A,@DPTR
MOV R7,A
; /*
; //芯片可配置选项
; WriteIO(RegClockQControl,0x0);
; WriteIO(RegClockQControl,0x40);
; delay(2);// wait approximately 50ms(>100us) - calibration in progress
; //ClearBitMask(RegClockQControl,0x40); // clear bit ClkQCalib for further calibration
; WriteIO(RegBitPhase,0xAD);// initialize bit phase
; WriteIO(RegRxThreshold,0xFF);// initialize minlevel
; //WriteIO(RegRxControl2,01);// disable auto power down
; WriteIO(RegTimerControl,0x0a);//TStartTxEnd=1,TStopRxEnd=1
; WriteIO(RegIRqPinConfig,0x3); // interrupt active low enable
; ClearBitMask(RegTxControl,0x03); // Tx2RF-En, Tx1RF-En disable
; delay(2); // Delay for 1 ms
; WriteIO(RegTxControl,0x5b);
; WriteIO(RegRxControl1,0x72);//38db
; WriteIO(RegRxControl2,0xC1);//41);//Power saving
; WriteIO(RegDecoderControl,0x28);
; WriteIO(RegTimerClock,0x07);
; WriteIO(RegRxThreshold,0xff);////
; WriteIO(RegFIFOLevel,0x01);///
; //初始状态
; WriteIO(RegInterruptRq,0x7F);//clear all inter
; //WriteIO(RegInterruptEn,0xFF);//enable all interrupts
; WriteIO(RegCommand,PCD_IDLE);
; SetBitMask(RegControl,0x01);//FlushFIFO
; SetBitMask(RegControl,0x04);//StopTimer
; WriteIO(RegInterruptEn,0x7f);
; WriteIO(RegInterruptEn,0x88);//RC500只开接收中断
; */
; }
; SOURCE LINE # 581
?C0051:
RET
; END OF M500PcdInit
;
; /********************************
; * mfrc500 reset *
; * ms: time between clr and set *
; ********************************/
; void M500PcdRfReset(uchar ms)
RSEG ?PR?_M500PcdRfReset?MFRC500
_M500PcdRfReset:
USING 0
; SOURCE LINE # 587
MOV DPTR,#ms?860
MOV A,R7
MOVX @DPTR,A
; {
; SOURCE LINE # 588
; ClearBitMask(RegTxControl,0x03);
; SOURCE LINE # 589
MOV R5,#03H
MOV R7,#011H
LCALL _ClearBitMask
;
; if(ms > 0)
; SOURCE LINE # 591
MOV DPTR,#ms?860
MOVX A,@DPTR
MOV R7,A
SETB C
SUBB A,#00H
JC ?C0053
; {
; SOURCE LINE # 592
; delay(ms + 1);
; SOURCE LINE # 593
MOV A,R7
ADD A,#01H
MOV R7,A
CLR A
RLC A
MOV R6,A
LCALL _delay
; SetBitMask(RegTxControl,0x03);
; SOURCE LINE # 594
MOV R5,#03H
MOV R7,#011H
LCALL _SetBitMask
; }
; SOURCE LINE # 595
; }
; SOURCE LINE # 596
?C0053:
RET
; END OF _M500PcdRfReset
;
; uchar M500PcdReset(void)
RSEG ?PR?M500PcdReset?MFRC500
M500PcdReset:
USING 0
; SOURCE LINE # 598
; {
; SOURCE LINE # 599
; unsigned int starttime;
; unsigned char rdval = 0;
; SOURCE LINE # 601
CLR A
MOV DPTR,#rdval?962
MOVX @DPTR,A
;
; // first reset by the rst pin
; M500Reset();
; SOURCE LINE # 604
SETB P2_7
MOV R7,#064H
MOV R6,A
LCALL _delay
CLR P2_7
;
; // wait until reset command recognized
; starttime = GetTickCount();
; SOURCE LINE # 607
LCALL GetTickCount
MOV DPTR,#starttime?961
MOV A,R6
MOVX @DPTR,A
INC DPTR
MOV A,R7
MOVX @DPTR,A
?C0054:
; while (ReadRawIO(RegCommand) & 0x3F != 0x3F)
; SOURCE LINE # 608
; {
; SOURCE LINE # 609
; if(GetTickCount() - starttime >= 200)
; SOURCE LINE # 610
; {
; SOURCE LINE # 611
; #ifndef FORCE_RESET
; return MI_RESETERR;
; SOURCE LINE # 613
; #else
; rdval = MI_RESETERR;
; break;
; #endif
; }
; SOURCE LINE # 618
; }
; SOURCE LINE # 619
?C0055:
;
; // while reset sequence in progress
; starttime = GetTickCount();
; SOURCE LINE # 622
LCALL GetTickCount
MOV DPTR,#starttime?961
MOV A,R6
MOVX @DPTR,A
INC DPTR
MOV A,R7
MOVX @DPTR,A
?C0058:
; while (ReadRawIO(RegCommand) & 0x3F)
; SOURCE LINE # 623
MOV R7,#01H
LCALL _ReadRawIO
MOV A,R7
ANL A,#03FH
JZ ?C0059
; {
; SOURCE LINE # 624
; if(GetTickCount() - starttime >= 200)
; SOURCE LINE # 625
LCALL GetTickCount
MOV DPTR,#starttime?961
MOVX A,@DPTR
MOV R4,A
INC DPTR
MOVX A,@DPTR
MOV R5,A
CLR C
MOV A,R7
SUBB A,R5
MOV R7,A
MOV A,R6
SUBB A,R4
MOV R6,A
CLR C
MOV A,R7
SUBB A,#0C8H
MOV A,R6
SUBB A,#00H
JC ?C0058
; {
; SOURCE LINE # 626
; #ifndef FORCE_RESET
; return MI_RESETERR;
; SOURCE LINE # 628
MOV R7,#011H
RET
; #else
; rdval = MI_RESETERR;
; break;
; #endif
; }
; SOURCE LINE # 633
; }
; SOURCE LINE # 634
?C0059:
;
; WriteRawIO(RegPage,0x80); // Dummy access in order to determine the bus
; SOURCE LINE # 636
MOV R5,#080H
CLR A
MOV R7,A
LCALL _WriteRawIO
; // configuration
; // necessary read access
; // after first write access, the returned value
; // should be zero ==> interface recognized
; if (ReadRawIO(RegCommand) != 0x00)
; SOURCE LINE # 641
MOV R7,#01H
LCALL _ReadRawIO
MOV A,R7
JZ ?C0061
; {
; SOURCE LINE # 642
; rdval = MI_INTERFACEERR;
; SOURCE LINE # 643
MOV DPTR,#rdval?962
MOV A,#012H
MOVX @DPTR,A
; }
; SOURCE LINE # 644
?C0061:
;
; WriteRawIO(RegPage,0x00); // configure to linear address mode
; SOURCE LINE # 646
CLR A
MOV R5,A
MOV R7,A
LCALL _WriteRawIO
;
; return rdval;
; SOURCE LINE # 648
MOV DPTR,#rdval?962
MOVX A,@DPTR
MOV R7,A
; }
; SOURCE LINE # 649
?C0057:
RET
; END OF M500PcdReset
;
; /********************************
; * SET DEFAULT COMM ATTRIB *
; ********************************/
; uchar M500PcdSetDefaultAttrib(void)
RSEG ?PR?M500PcdSetDefaultAttrib?MFRC500
M500PcdSetDefaultAttrib:
USING 0
; SOURCE LINE # 654
; {
; SOURCE LINE # 655
; uchar status = MI_OK;
; SOURCE LINE # 656
;---- Variable 'status?1063' assigned to Register 'R7' ----
CLR A
MOV R7,A
; /*
; WriteRawIO(RegTimerClock,0x07);
; WriteRawIO(RegInterruptRq,0x7F);//clear all inter
;
; SetBitMask(RegControl,0x04); //StopTimer
; WriteRawIO(RegTxControl,0x5b);
;
; //WriteRawRC(RegInterruptEn,0x7F);//disable all interrupts
; //WriteRawRC(RegInterruptEn,0x88);
; //WriteRawRC(RegChannelRedundancy,0x00); //no parity, no crc ; 03, en parity
; //ClearBitMask(RegControl,0x08); // disable crypto 1 unit
; //WriteRawRC(RegBitFraming,0x07); // set TxLastBits to 7
;
; WriteRawIO(RegInterruptEn,0x7f);
; //WriteRawRC(RegInterruptEn,0x88);
;
; FlushFIFO();*/
; return status;
; SOURCE LINE # 674
; }
; SOURCE LINE # 675
?C0062:
RET
; END OF M500PcdSetDefaultAttrib
;
; /********************************
; * mfrc500 request card *
; * req_code: type of request *
; * atq: answer to request *
; ********************************/
; uchar M500Request(uchar req_code, uchar *atq)
RSEG ?PR?_M500Request?MFRC500
_M500Request:
USING 0
; SOURCE LINE # 682
MOV DPTR,#req_code?1164
MOV A,R7
MOVX @DPTR,A
INC DPTR
MOV A,R3
MOVX @DPTR,A
INC DPTR
MOV A,R2
MOVX @DPTR,A
INC DPTR
MOV A,R1
MOVX @DPTR,A
; {
; SOURCE LINE # 683
;
; uchar idata status = MI_OK;
; SOURCE LINE # 685
CLR A
MOV R0,#LOW (status?1166)
MOV @R0,A
;
; M500PcdSetDefaultAttrib();
; SOURCE LINE # 687
LCALL M500PcdSetDefaultAttrib
;
; // ClearBitMask(RegTxControl,0x03); // 050418
; // delay(2); // same as upon
;
; WriteIO(RegChannelRedundancy,0x03); // 03
; SOURCE LINE # 692
MOV R5,#03H
MOV R7,#022H
LCALL _WriteIO
; ClearBitMask(RegControl,0x08);
; SOURCE LINE # 693
LCALL L?0396
; WriteIO(RegBitFraming,0x07);
; SOURCE LINE # 694
MOV R5,#07H
MOV R7,#0FH
LCALL _WriteIO
;
; // M500PcdRfReset(3); ///////////// 050418
;
; ResetInfo(&MInfo);
; SOURCE LINE # 698
MOV R3,#01H
MOV R2,#HIGH (MInfo)
MOV R1,#LOW (MInfo)
LCALL _ResetInfo
; SndBuffer[0] = req_code;
; SOURCE LINE # 699
MOV DPTR,#req_code?1164
MOVX A,@DPTR
MOV DPTR,#SndBuffer
MOVX @DPTR,A
; MInfo.nBytesToSend = 1;
; SOURCE LINE # 700
MOV A,#01H
; M500PcdSetTmo(3); // 2 050418
; SOURCE LINE # 701
LCALL L?0400
; status = M500PcdCmd(PCD_TRANSCEIVE, SndBuffer, RcvBuffer, &MInfo);
; SOURCE LINE # 702
LCALL L?0394
MOV R0,#LOW (status?1166)
MOV A,R7
MOV @R0,A
;
; if (status)
; SOURCE LINE # 704
JZ ?C0063
; {
; SOURCE LINE # 705
; *atq = 0;
; SOURCE LINE # 706
MOV DPTR,#atq?1165
MOVX A,@DPTR
MOV R3,A
INC DPTR
MOVX A,@DPTR
MOV R2,A
INC DPTR
MOVX A,@DPTR
MOV R1,A
CLR A
LCALL ?C?CSTPTR
; }
; SOURCE LINE # 707
SJMP ?C0064
?C0063:
; else
; {
; SOURCE LINE # 709
; if (MInfo.nBitsReceived != 16)
; SOURCE LINE # 710
MOV DPTR,#MInfo+05H
MOVX A,@DPTR
JNZ ?C0350
INC DPTR
MOVX A,@DPTR
XRL A,#010H
?C0350:
JZ ?C0065
; {
; SOURCE LINE # 711
; *atq = 0;
; SOURCE LIN⌨️ 快捷键说明
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