📄 mfrc500.src
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MOV R6,A
SETB C
MOV A,R7
SUBB A,#0A4H
MOV A,R6
SUBB A,#01H
JC ?C0030
?C0031:
; || (GetTickCount() - starttime > 420))); // wait for cmd completion or timeout
;
; // disableme(); // disable interrupt just when cmd complete, 050517
;
; WriteIO(RegInterruptEn,0x7F); // disable all interrupts
; SOURCE LINE # 224
MOV R5,#07FH
MOV R7,#06H
LCALL _WriteIO
; WriteIO(RegInterruptRq,0x7F); // clear all interrupt requests
; SOURCE LINE # 225
MOV R5,#07FH
MOV R7,#07H
LCALL _WriteIO
; SetBitMask(RegControl,0x04); // stop timer now
; SOURCE LINE # 226
MOV R5,#04H
MOV R7,#09H
LCALL _SetBitMask
; WriteIO(RegCommand,PCD_IDLE); // reset command register
; SOURCE LINE # 227
CLR A
MOV R5,A
MOV R7,#01H
LCALL _WriteIO
;
; if (!(MpIsrInfo->irqSource & waitFor)) // reader has not terminated
; SOURCE LINE # 229
MOV DPTR,#MpIsrInfo
MOVX A,@DPTR
MOV R3,A
INC DPTR
MOVX A,@DPTR
MOV R2,A
INC DPTR
MOVX A,@DPTR
MOV R1,A
MOV DPTR,#07H
LCALL ?C?CLDOPTR
ANL A,waitFor?556
JNZ ?C0032
; { // timer 3 expired
; SOURCE LINE # 230
; status = MI_ACCESSTIMEOUT;
; SOURCE LINE # 231
MOV status?554,#013H
; }
; SOURCE LINE # 232
SJMP ?C0033
?C0032:
; else
; status = MpIsrInfo->status; // set status
; SOURCE LINE # 234
MOV DPTR,#01H
LCALL ?C?CLDOPTR
MOV status?554,A
?C0033:
;
; if (status == MI_OK) // no timeout error occured
; SOURCE LINE # 236
MOV A,status?554
JZ $ + 5H
LJMP ?C0034
; {
; SOURCE LINE # 237
; if (tmpStatus = (ReadIO(RegErrorFlag) & 0x17/*0x1f*/)) // error occured
; SOURCE LINE # 238
MOV R7,#0AH
LCALL _ReadIO
MOV A,R7
ANL A,#017H
MOV tmpStatus?552,A
JZ ?C0035
; {
; SOURCE LINE # 239
; if (tmpStatus & 0x01) // collision detected
; SOURCE LINE # 240
JNB ACC.0,?C0036
; {
; SOURCE LINE # 241
; info->collPos = ReadIO(RegCollpos); // read collision position
; SOURCE LINE # 242
MOV R7,#0BH
LCALL _ReadIO
MOV DPTR,#info?551
MOVX A,@DPTR
MOV R3,A
INC DPTR
MOVX A,@DPTR
MOV R2,A
INC DPTR
MOVX A,@DPTR
MOV R1,A
MOV DPTR,#08H
MOV A,R7
LCALL ?C?CSTOPTR
; status = MI_COLLERR;
; SOURCE LINE # 243
MOV status?554,#010H
; }
; SOURCE LINE # 244
SJMP ?C0037
?C0036:
; else
; {
; SOURCE LINE # 246
; info->collPos = 0;
; SOURCE LINE # 247
MOV DPTR,#info?551
MOVX A,@DPTR
MOV R3,A
INC DPTR
MOVX A,@DPTR
MOV R2,A
INC DPTR
MOVX A,@DPTR
MOV R1,A
MOV DPTR,#08H
CLR A
LCALL ?C?CSTOPTR
; if (tmpStatus & 0x02) // parity error
; SOURCE LINE # 248
MOV A,tmpStatus?552
JNB ACC.1,?C0037
; {
; SOURCE LINE # 249
; status = MI_PARITYERR;
; SOURCE LINE # 250
MOV status?554,#04H
; }
; SOURCE LINE # 251
; }
; SOURCE LINE # 252
?C0037:
;
; if (tmpStatus & 0x04) // framing error
; SOURCE LINE # 254
MOV A,tmpStatus?552
JNB ACC.2,?C0039
; {
; SOURCE LINE # 255
; status = MI_FRAMINGERR;
; SOURCE LINE # 256
MOV status?554,#0EH
; }
; SOURCE LINE # 257
?C0039:
; if (tmpStatus & 0x10) // FIFO overflow
; SOURCE LINE # 258
MOV A,tmpStatus?552
JNB ACC.4,?C0040
; {
; SOURCE LINE # 259
; FlushFIFO();
; SOURCE LINE # 260
LCALL FlushFIFO
; status = MI_OVFLERR;
; SOURCE LINE # 261
MOV status?554,#0DH
; }
; SOURCE LINE # 262
?C0040:
; if (tmpStatus & 0x08) //CRC error
; SOURCE LINE # 263
MOV A,tmpStatus?552
JNB ACC.3,?C0041
; {
; SOURCE LINE # 264
; status = MI_CRCERR;
; SOURCE LINE # 265
MOV status?554,#02H
; }
; SOURCE LINE # 266
?C0041:
; if (status == MI_OK)
; SOURCE LINE # 267
MOV A,status?554
JNZ ?C0035
; status = MI_NY_IMPLEMENTED;
; SOURCE LINE # 268
MOV status?554,#014H
; // key error occures always, because of
; // missing crypto 1 keys loaded
; }
; SOURCE LINE # 271
?C0035:
; // if the last command was TRANSCEIVE, the number of
; // received bits must be calculated - even if an error occured
; if (cmdcode == PCD_TRANSCEIVE || cmdcode == PCD_RECEIVE) ////////////////////
; SOURCE LINE # 274
MOV DPTR,#cmdcode?548
MOVX A,@DPTR
MOV R7,A
XRL A,#01EH
JZ ?C0044
MOV A,R7
XRL A,#016H
JNZ ?C0029
?C0044:
; {
; SOURCE LINE # 275
; // number of bits in the last byte
; lastBits = ReadIO(RegSecondaryStatus) & 0x07;
; SOURCE LINE # 277
MOV R7,#05H
LCALL _ReadIO
MOV A,R7
ANL A,#07H
MOV lastBits?553,A
; if (lastBits)
; SOURCE LINE # 278
JZ ?C0045
; info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
; SOURCE LINE # 279
MOV DPTR,#info?551
MOVX A,@DPTR
MOV R3,A
INC DPTR
MOVX A,@DPTR
MOV R2,A
INC DPTR
MOVX A,@DPTR
MOV R1,A
MOV DPTR,#04H
LCALL ?C?CLDOPTR
ADD A,#0FFH
MOV R7,A
CLR A
ADDC A,#0FFH
MOV R6,A
MOV A,R7
MOV R0,#03H
?C0349:
CLR C
RLC A
XCH A,R6
RLC A
XCH A,R6
DJNZ R0,?C0349
MOV R4,#00H
ADD A,lastBits?553
MOV R7,A
MOV A,R4
ADDC A,R6
MOV DPTR,#05H
SJMP ?C0383
?C0045:
; else
; info->nBitsReceived += info->nBytesReceived * 8;
; SOURCE LINE # 281
MOV DPTR,#info?551
MOVX A,@DPTR
MOV R3,A
INC DPTR
MOVX A,@DPTR
MOV R2,A
INC DPTR
MOVX A,@DPTR
MOV R1,A
MOV DPTR,#04H
LCALL ?C?CLDOPTR
MOV B,#08H
MUL AB
MOV R7,A
MOV DPTR,#05H
MOV A,B
?C0383:
MOV B,R7
LCALL ?C?IILDOPTR
; }
; SOURCE LINE # 282
; }
; SOURCE LINE # 283
SJMP ?C0029
?C0034:
; else
; {
; SOURCE LINE # 285
; info->collPos = 0x00;
; SOURCE LINE # 286
MOV DPTR,#info?551
MOVX A,@DPTR
MOV R3,A
INC DPTR
MOVX A,@DPTR
MOV R2,A
INC DPTR
MOVX A,@DPTR
MOV R1,A
MOV DPTR,#08H
CLR A
LCALL ?C?CSTOPTR
; }
; SOURCE LINE # 287
; }
; SOURCE LINE # 288
?C0029:
; disableme();
; SOURCE LINE # 289
CLR EX0
;
; MpIsrInfo = 0; // reset interface variables for ISR
; SOURCE LINE # 291
MOV DPTR,#MpIsrInfo
CLR A
MOVX @DPTR,A
INC DPTR
MOVX @DPTR,A
INC DPTR
MOVX @DPTR,A
; MpIsrOut = 0;
; SOURCE LINE # 292
MOV R1,A
INC DPTR
XCH A,R1
MOVX @DPTR,A
INC DPTR
MOVX @DPTR,A
INC DPTR
MOV A,R1
MOVX @DPTR,A
; MpIsrIn = 0;
; SOURCE LINE # 293
INC DPTR
CLR A
MOVX @DPTR,A
INC DPTR
MOVX @DPTR,A
INC DPTR
MOVX @DPTR,A
; return status;
; SOURCE LINE # 294
MOV R7,status?554
; }
; SOURCE LINE # 295
?C0048:
RET
; END OF _M500PcdCmd
; #else
; //////////////////////////////////////////////////////////////////////
; // W R I T E A P C D C O M M A N D
; ///////////////////////////////////////////////////////////////////////
; char M500PcdCmd(unsigned char cmd,
; volatile unsigned char* send,
; volatile unsigned char* rcv,
; volatile MfCmdInfo *info)
; {
; char status = MI_OK;
; char tmpStatus ;
; unsigned char lastBits;
;
; unsigned char irqEn = 0x00;
; unsigned char waitFor = 0x00;
; unsigned char timerCtl = 0x00;
;
; WriteIO(RegInterruptEn,0x7F); // disable all interrupts
; WriteIO(RegInterruptRq,0x7F); // reset interrupt requests
; WriteIO(RegCommand,PCD_IDLE); // terminate probably running command
;
; FlushFIFO(); // flush FIFO buffer
;
; // save info structures to module pointers
; MpIsrInfo = info;
; MpIsrOut = send;
; MpIsrIn = rcv;
;
; info->irqSource = 0x0; // reset interrupt flags
;
; enableme();
;
; // depending on the command code, appropriate interrupts are enabled (irqEn)
; // and the commit interrupt is choosen (waitFor).
; switch(cmd)
; {
; case PCD_IDLE: // nothing else required
; irqEn = 0x00;
; waitFor = 0x00;
; break;
; case PCD_WRITEE2: // LoAlert and TxIRq
; irqEn = 0x11;
; waitFor = 0x10;
; break;
; case PCD_READE2: // HiAlert, LoAlert and IdleIRq
; irqEn = 0x07;
; waitFor = 0x04;
; break;
; case PCD_LOADCONFIG: // IdleIRq and LoAlert
; case PCD_LOADKEYE2: // IdleIRq and LoAlert
; case PCD_AUTHENT1: // IdleIRq and LoAlert
; irqEn = 0x05;
; waitFor = 0x04;
; break;
; case PCD_CALCCRC: // LoAlert and TxIRq
; irqEn = 0x11;
; waitFor = 0x10;
; break;
; case PCD_AUTHENT2: // IdleIRq
; irqEn = 0x04;
; waitFor = 0x04;
; break;
; case PCD_RECEIVE: // HiAlert and IdleIRq
; info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
; irqEn = 0x06;
; waitFor = 0x04;
; break;
; case PCD_LOADKEY: // IdleIRq
; irqEn = 0x05;
; waitFor = 0x04;
; break;
; case PCD_TRANSMIT: // LoAlert and IdleIRq
; irqEn = 0x05;
; waitFor = 0x04;
; break;
; case PCD_TRANSCEIVE: // TxIrq, RxIrq, IdleIRq and LoAlert
; info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
; irqEn = 0x3D;
; waitFor = 0x04;
; break;
; default:
; status = MI_UNKNOWN_COMMAND;
; }
; if (status == MI_OK)
; {
; // Initialize uC Timer for global Timeout management
; irqEn |= 0x20; // always enable timout irq
; waitFor |= 0x20; // always wait for timeout
; WriteIO(RegInterruptEn,irqEn | 0x80); //necessary interrupts are enabled // count up from 1
;
; WriteIO(RegCommand,cmd); //start command
; starttime = GetTickCount();
;
; // wait for commmand completion
; // a command is completed, if the corresponding interrupt occurs
; // or a timeout is signaled
;
; while (!(MpIsrInfo->irqSource & waitFor
; || T3IR)); // wait for cmd completion or timeout
;
; WriteIO(RegInterruptEn,0x7F); // disable all interrupts
; WriteIO(RegInterruptRq,0x7F); // clear all interrupt requests
; SetBitMask(RegControl,0x04); // stop timer now
;
; GT_vStopTmr(TIMER_4);
; GT_vStopTmr(TIMER_3);
; LED_OFF;
;
; T3IR = 0;
; WriteIO(RegCommand,PCD_IDLE); // reset command register
;
; if (!(MpIsrInfo->irqSource & waitFor)) // reader has not terminated
; { // timer 3 expired
; status = MI_ACCESSTIMEOUT;
; }
; else
; status = MpIsrInfo->status; // set status
;
; if (status == MI_OK) // no timeout error occured
; {
; if ((tmpStatus = (ReadIO(RegErrorFlag) & 0x17))) // error occured
; {
; if (tmpStatus & 0x01) // collision detected
; {
; info->collPos = ReadIO(RegCollPos); // read collision position
; status = MI_COLLERR;
; }
; else
; {
; info->collPos = 0;
; if (tmpStatus & 0x02) // parity error
; {
; status = MI_PARITYERR;
; }
; }
; if (tmpStatus & 0x04) // framing error
; {
; status = MI_FRAMINGERR;
; }
; if (tmpStatus & 0x10) // FIFO overflow
; {
; FlushFIFO();
; status = MI_OVFLERR;
; }
; if (tmpStatus & 0x08) // CRC error
; {
; status = MI_CRCERR;
; }
; if (status == MI_OK)
; status = MI_NY_IMPLEMENTED;
; // key error occures always, because of
; // missing crypto 1 keys loaded
; }
; // if the last command was TRANSCEIVE, the number of
; // received bits must be calculated - even if an error occured
; if (cmd == PCD_TRANSCEIVE || cmd == PCD_RECEIVE)
; {
; // number of bits in the last byte
; lastBits = ReadIO(RegSecondaryStatus) & 0x07;
; if (lastBits)
; info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
; else
; info->nBitsReceived += info->nBytesReceived * 8;
; }
; }
; else
; {
; info->collPos = 0x00;
; }
; }
;
; READER_INT_DISABLE;
;
; PcdIsrFct = EmptyPcdIsrFct; // reset the ISR-Function pointer to
; // an empty function body
; // do this before clearing the Mp XXXX variables
;
; MpIsrInfo = 0; // reset interface variables for ISR
; MpIsrOut = 0;
; MpIsrIn = 0;
; return status;
; }
; #endif
;
; /********************************
; * set mfrc500 receive gain *
; ********************************/
; void M500SetRcvGain(uchar gain)
RSEG ?PR?_M500SetRcvGain?MFRC500
_M500SetRcvGain:
USING 0
; SOURCE LINE # 483
;---- Variable 'gain?658' assigned to Register 'R7' ----
; {
; SOURCE LINE # 484
; if(gain > 3)
; SOURCE LINE # 485
MOV A,R7
SETB C
SUBB A,#03H
JC ?C0049
; gain = 3;
; SOURCE LINE # 486
MOV R7,#03H
?C0049:
; RxGain = gain + 0x70;
; SOURCE LINE # 487
MOV A,R7
ADD A,#070H
MOV DPTR,#RxGain
MOVX @DPTR,A
MOV R5,A
;
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