iquant_vhd.vhd

IDCT - xlinix design in vhdl

         qdct_out_mag6 <= '0';    
         qdct_out_mag7 <= '0';    
         --macroblock_type_reg1 <= 1'b0; 
         
         macroblock_type_reg2 <= '0';    
         macroblock_type_reg3 <= '0';    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         qdct_out_reg <= "0" & temp4;    
         qdct_out_mag2 <= qdct_out(11);    
         qdct_out_mag3 <= qdct_out_mag2;    
         qdct_out_mag4 <= qdct_out_mag3;    
         qdct_out_mag5 <= qdct_out_mag4;    
         qdct_out_mag6 <= qdct_out_mag5;    
         qdct_out_mag7 <= qdct_out_mag6;    
         --macroblock_type_reg1 <= macroblock_type; 
         
         macroblock_type_reg2 <= macroblock_type_reg1;    
         macroblock_type_reg3 <= macroblock_type_reg2;    
      END IF;
   END PROCESS;
   --***************************************************************************
   case_wire <= macroblock_type_reg2 & qdct_out_comp & qdct_out_mag2 ;

   -- Of the 13 bits, 12 bits are magnitude and the msb is for sign 
   --if macroblock = intra ie., '0', quant shift = 2*QDCT + 0
   -- if macroblock = intra ie., '0', quant shift = 2*QDCT + 0
   -- if macroblock = non intra ie., '1', quant shift = 2*QDCT + k where
   -- k = 0 if QDCT =0, k = 1 if QDCT is +ve and k = -1 if QDCT = -ve 
   
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         quant_shift <= "0000000000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         CASE case_wire IS
            WHEN "000" =>
                     quant_shift <= qdct_out_reg & '0';    
            WHEN "001" =>
                     quant_shift <= qdct_out_reg & '0';    
            WHEN "010" =>
                     quant_shift <= qdct_out_reg & '0';    
            WHEN "011" =>
                     quant_shift <= qdct_out_reg & '0';    
            WHEN "110" =>
                     quant_shift <= qdct_out_reg & '0';    
            WHEN "111" =>
                     quant_shift <= qdct_out_reg & '0';    
            WHEN "100" =>
                     quant_shift <= qdct_out_reg & '1';    
            WHEN "101" =>
                     quant_shift <= qdct_out_reg & '0' - 
                     "0000000000001";    
            WHEN OTHERS =>
                     NULL;
            
         END CASE;
      END IF;
   END PROCESS;

   
   --***************************************************************************
   -- [Qmatrix*(qscale/32)] => 8bits * 10bits(2,8decimal) = 18bits (last 8 bits being decimal). 
   --  [Qmatrix*(qscale/32)] => 8bits * 10bits(2,8decimal) = 18bits (last 8 bits being decimal). 
   -- Since the last 3 digits of q_scale_mem are always '0', the multiplication and result 
   -- could also be looked at as 8bits * 7bits(2,5 decimal) = 15bits with the last 5 bits being decimal.
   -- : pipe3 for q matrix and qscale. Prod1 registered once to match the 4 pipe stages of
   -- quant_shift into the next multiplier
   
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         prod1 <= (OTHERS => '0');    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         --if (rdy_in == 1'b1)
         
         IF (load_intra_qmatrix_reg3 = '0' AND 
         load_non_intra_qmatrix_reg3 = '0') THEN
            prod1 <= (def_q_mem_reg * q_scale_mem(9 DOWNTO 3)
            );    
         ELSE
            prod1 <= (q_value_new_out * q_scale_mem(9 DOWNTO 
            3));    
         END IF;
      END IF;
   END PROCESS;

   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         prod1_reg <= "000000000000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         prod1_reg <= prod1;    --  last 5 bits decimal 
      END IF;
   END PROCESS;

   --***************************************************************************
   -- (2*quantised input + k) * qscale/32 * Qmatrix . 
   --  (2*quantised input + k) * qscale/32 * Qmatrix . 
   --  13 bits * 18 bits = 31 bits with the last 8 bits being decimal
   --  or 13 bits * 15 bits = 28 bits with last 5 bits being decimal.
   -- Of the 13 bits, msb is sign bit. This 13 bits are sign extended to 17 bits.
   -- Sign extension is done to retain the correct sign at the output of prod2
   -- which is 28 bits wide. Sign extension is done only to 17 bits so that embedded
   -- mulipliers can be used for Virtex family
   
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         prod2 <= (OTHERS => '0');    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (rdy_in = '1') THEN
            prod2 <= (prod1 * quant_shift(11 DOWNTO 0));    
            --15 bits * 12 bits = 27 bits with 5 decimal
            -- 15 bits * 12 bits = 27 bits with 5 decimal
            --                   msb of quant_shift is sign bit and is accounted for
            --                   in prod2_sign
            
            
         ELSE
            
         END IF;
      END IF;
   END PROCESS;
   temp5 <= (prod2(26 DOWNTO 5) + "0000000000000000000001") WHEN 
   prod2(4) = '1' ELSE prod2(26 DOWNTO 5);

   --***************************************************************************
   -- rounding and saturation to 2047 (111,1111,1111) to -2048 (1000,0000,0000) 
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         prod2_rnd <= "0000000000000000000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (rdy_in = '1') THEN
            prod2_rnd <= temp5;    
            -- rounding up decimal.(35:8) or (32:5) 
            
         END IF;
      END IF;
   END PROCESS;
   temp6 <= ( not(prod2_rnd) + '1') WHEN (qdct_out_mag5) = '1' ELSE 
   prod2_rnd;
   temp7 <= '1' WHEN (prod2_sign(20 DOWNTO 11) = "0000000000") ELSE 
   '0';
   temp8 <= '1' WHEN (prod2_sign(20 DOWNTO 11) = "1111111111") ELSE 
   '0';

   --***************************************************************************
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         prod2_sign <= "0000000000000000000000";    
         prod2_rnd_pos <= '0';    
         prod2_rnd_neg <= '0';    
         prod2_sign_reg <= "0000000000000000000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         prod2_sign <= temp6;    
         prod2_sign_reg <= prod2_sign;    
         prod2_rnd_pos <= temp7;    
         prod2_rnd_neg <= temp8;    
      END IF;
   END PROCESS;
   temp9 <= '1' & prod2_sign_reg(10 DOWNTO 0) WHEN (prod2_rnd_neg) 
   = '1' ELSE "100000000000";
   temp10 <= '0' & prod2_sign_reg(10 DOWNTO 0) WHEN (prod2_rnd_pos) 
   = '1' ELSE "011111111111";

   --***************************************************************************
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         prod_sat <= "000000000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         CASE prod2_sign_reg(21) IS
            WHEN '1' =>
                     prod_sat <= temp9;    
            WHEN '0' =>
                     prod_sat <= temp10;    
            WHEN OTHERS =>
                     NULL;
            
         END CASE;
      END IF;
   END PROCESS;

   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         prod_sat_reg <= "000000000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         prod_sat_reg <= prod_sat;    
      END IF;
   END PROCESS;

   --***************************************************************************
   -- mismatch control. If sum of 64 coefficients is odd, no correction. If it
   --  mismatch control. If sum of 64 coefficients is odd, no correction. If it
   -- is even, then F[7,7] = (prod2[7,7] - 1 ) if prod2[7,7] is odd else 
   -- F[7,7] = (prod2[7,7] + 1 ) . The lsb of the sum can be xored to find out if the sum 
   -- of all coefficient is even or odd 
   
   PROCESS (CLK, RST)
      --VARIABLE Q_cnt64_temp  : integer;
   BEGIN
      IF (RST = '1') THEN
         quant_sum <= "00";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (rdy_in = '1' AND cnt64 = "0001011") THEN
            FOR Q_cnt64 IN 1 TO 63 LOOP
               quant_sum <= quant_sum + prod2_sign_reg(0);    
            END LOOP;
            Q_cnt64 <= 1;    
         END IF;
      END IF;
	        --Q_cnt64 <= Q_cnt64_temp;
   END PROCESS;


   temp12 <= prod_sat(11 DOWNTO 1) & prod_sat(0) WHEN (quant_sum(0)) = 
   '1' ELSE prod_sat(11 DOWNTO 1) & NOT prod_sat(0);

   --***************************************************************************
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         prod_mismatch <= "000000000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (rdy_in = '1' AND cnt64 = "1000000") THEN
            prod_mismatch <= temp12;    
         END IF;
      END IF;
   END PROCESS;

   --***************************************************************************
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         q_out <= "000000000000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (rdy_in = '1') THEN
            IF (cnt64 = "1000000") THEN
               q_out <= prod_mismatch;    
            ELSE
               q_out <= prod_sat_reg;    
            END IF;
         END IF;
      END IF;
   END PROCESS;

   --***************************************************************************
   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         cnt12 <= "0000";    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (rdy_in = '1') THEN
            IF (cnt12 < "1011") THEN
               cnt12 <= cnt12 + "0001";    
            ELSE
               cnt12 <= "1011";    
            END IF;
         END IF;
      END IF;
   END PROCESS;

   PROCESS (CLK, RST)
   BEGIN
      IF (RST = '1') THEN
         iquant_rdy_out <= '0';    
      ELSIF (CLK'EVENT AND CLK = '1') THEN
         IF (cnt12 = "1011") THEN
            iquant_rdy_out <= '1';    
         ELSE
            iquant_rdy_out <= iquant_rdy_out;    
         END IF;
      END IF;
   END PROCESS;

END translated;