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-- store quant_scale_code/32 in q_scale_mem1 and q_scale_mem2. Q_scale_type is used to
-- store quant_scale_code/32 in q_scale_mem1 and q_scale_mem2. Q_scale_type is used to
-- choose between the 2 memories. For scale type 0, the min. value is 2/32 and max
-- value = 62/32. For scale type 1, the min value = 1/32 and max value = 112/32. : pipe1
qscale_mem_sel <= cnt_start & quant_scale_type_reg2 &
quant_scale_code_reg2 ;
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
CASE qscale_mem_sel IS
WHEN "1000001" => q_scale_mem <= "0000010000";
WHEN "1000010" => q_scale_mem <= "0000100000";
WHEN "1000011" => q_scale_mem <= "0000110000";
WHEN "1000100" => q_scale_mem <= "0001000000";
WHEN "1000101" => q_scale_mem <= "0001010000";
WHEN "1000110" => q_scale_mem <= "0001100000";
WHEN "1000111" => q_scale_mem <= "0001110000";
WHEN "1001000" => q_scale_mem <= "0010000000";
WHEN "1001001" => q_scale_mem <= "0010010000";
WHEN "1001010" => q_scale_mem <= "0010100000";
WHEN "1001011" => q_scale_mem <= "0010110000";
WHEN "1001100" => q_scale_mem <= "0011000000";
WHEN "1001101" => q_scale_mem <= "0011010000";
WHEN "1001110" => q_scale_mem <= "0011100000";
WHEN "1001111" => q_scale_mem <= "0011110000";
WHEN "1010000" => q_scale_mem <= "0100000000";
WHEN "1010001" => q_scale_mem <= "0100010000";
WHEN "1010010" => q_scale_mem <= "0100100000";
WHEN "1010011" => q_scale_mem <= "0100110000";
WHEN "1010100" => q_scale_mem <= "0101000000";
WHEN "1010101" => q_scale_mem <= "0101010000";
WHEN "1010110" => q_scale_mem <= "0101100000";
WHEN "1010111" => q_scale_mem <= "0101110000";
WHEN "1011000" => q_scale_mem <= "0110000000";
WHEN "1011001" => q_scale_mem <= "0110010000";
WHEN "1011010" => q_scale_mem <= "0110100000";
WHEN "1011011" => q_scale_mem <= "0110110000";
WHEN "1011100" => q_scale_mem <= "0111000000";
WHEN "1011101" => q_scale_mem <= "0111010000";
WHEN "1011110" => q_scale_mem <= "0111100000";
WHEN "1100001" => q_scale_mem <= "0000001000"; -- .03125
WHEN "1100010" => q_scale_mem <= "0000010000"; -- .0625
WHEN "1100011" => q_scale_mem <= "0000011000"; -- .09375
WHEN "1100100" => q_scale_mem <= "0000100000"; -- .125
WHEN "1100101" => q_scale_mem <= "0000101000"; -- .15625
WHEN "1100110" => q_scale_mem <= "0000110000"; -- .1875
WHEN "1100111" => q_scale_mem <= "0000111000"; -- .21875
WHEN "1101000" => q_scale_mem <= "0001000000"; -- .25
WHEN "1101001" => q_scale_mem <= "0001010000"; -- .3125
WHEN "1101010" => q_scale_mem <= "0001100000"; -- .375
WHEN "1101011" => q_scale_mem <= "0001110000"; -- .4375
WHEN "1101100" => q_scale_mem <= "0010000000"; -- .5
WHEN "1101101" => q_scale_mem <= "0010010000"; -- .5625
WHEN "1101110" => q_scale_mem <= "0010100000"; -- .625
WHEN "1101111" => q_scale_mem <= "0010110000"; -- .6875
WHEN "1110000" => q_scale_mem <= "0011000000"; -- .75
WHEN "1110001" => q_scale_mem <= "0011100000"; -- .875
WHEN "1110010" => q_scale_mem <= "0100000000"; -- 1
WHEN "1110011" => q_scale_mem <= "0100100000"; -- 1.125
WHEN "1110100" => q_scale_mem <= "0101000000"; -- 1.25
WHEN "1110101" => q_scale_mem <= "0101100000"; -- 1.375
WHEN "1110110" => q_scale_mem <= "0110000000"; -- 1.5
WHEN "1110111" => q_scale_mem <= "0110100000"; -- 1.625
WHEN "1111000" => q_scale_mem <= "0111000000"; -- 1.75
WHEN "1111001" => q_scale_mem <= "1000000000"; -- 2
WHEN "1111010" => q_scale_mem <= "1001000000"; -- 2.25
WHEN "1111011" => q_scale_mem <= "1010000000"; -- 2.5
WHEN "1111100" => q_scale_mem <= "1011000000"; -- 2.75
WHEN "1111101" => q_scale_mem <= "1100000000"; -- 3
WHEN "1111110" => q_scale_mem <= "1101000000"; -- 3.25
WHEN "1111111" => q_scale_mem <= "1110000000";
WHEN OTHERS => q_scale_mem <= "0000000000";
END CASE;
END IF;
END PROCESS;
--***************************************************************************
-- register qscale for 64 clks. This is done to make sure that all the 64
-- register qscale for 64 clks. This is done to make sure that all the 64
-- DCT coefficients see the same qscale: pipe2
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
qscale_reg <= "0000000000";
ELSIF (CLK'EVENT AND CLK = '1') THEN
qscale_reg <= q_scale_mem;
END IF;
END PROCESS;
--***************************************************************************
def_qmem_sel <= cnt_start & macroblock_type_reg1 & cnt64b ;
-- Two 64x8 memories to store the default intra and non-intra Qmatrix (q_value_def) .
-- Two 64x8 memories to store the default intra and non-intra Qmatrix (q_value_def) .
-- Values are NOT stored in zig-zag order: pipe1
PROCESS (RST, CLK)
BEGIN
IF (RST = '1') THEN
def_q_mem <= (OTHERS => '0');
ELSIF (CLK'EVENT AND CLK = '1') THEN
CASE def_qmem_sel IS
WHEN "101000000" => def_q_mem <= "00001000"; -- zig_zag 8'd 8; end
WHEN "100000001" => def_q_mem <= "00010000"; -- zig_zag8'd 16; end
WHEN "100000010" => def_q_mem <= "00010011"; -- zig_zag8'd 16; end
WHEN "100000011" => def_q_mem <= "00010110"; -- zig_zag8'd 19; end
WHEN "100000100" => def_q_mem <= "00011010"; -- zig_zag8'd 16; end
WHEN "100000101" => def_q_mem <= "00011011"; -- zig_zag8'd 19; end
WHEN "100000110" => def_q_mem <= "00011101"; -- zig_zag8'd 22; end
WHEN "100000111" => def_q_mem <= "00100010"; -- zig_zag8'd 22; end
WHEN "100001000" => def_q_mem <= "00010000"; -- zig_zag8'd 22; end
WHEN "100001001" => def_q_mem <= "00010000"; -- zig_zag8'd 22; end
WHEN "100001010" => def_q_mem <= "00010110"; -- zig_zag8'd 22; end
WHEN "100001011" => def_q_mem <= "00011000"; -- zig_zag8'd 22; end
WHEN "100001100" => def_q_mem <= "00011011"; -- zig_zag8'd 26; end
WHEN "100001101" => def_q_mem <= "00011101"; -- zig_zag8'd 24; end
WHEN "100001110" => def_q_mem <= "00100010"; -- zig_zag8'd 26; end
WHEN "100001111" => def_q_mem <= "00100101"; -- zig_zag8'd 27; end
WHEN "100010000" => def_q_mem <= "00010011"; -- zig_zag8'd 27; end
WHEN "100010001" => def_q_mem <= "00010110"; -- zig_zag8'd 27; end
WHEN "100010010" => def_q_mem <= "00011010"; -- zig_zag8'd 26; end
WHEN "100010011" => def_q_mem <= "00011011"; -- zig_zag8'd 26; end
WHEN "100010100" => def_q_mem <= "00011101"; -- zig_zag8'd 26; end
WHEN "100010101" => def_q_mem <= "00100010"; -- zig_zag8'd 26; end
WHEN "100010110" => def_q_mem <= "00100010"; -- zig_zag8'd 27; end
WHEN "100010111" => def_q_mem <= "00100110"; -- zig_zag8'd 27; end
WHEN "100011000" => def_q_mem <= "00010110"; -- zig_zag8'd 27; end
WHEN "100011001" => def_q_mem <= "00010110"; -- zig_zag8'd 29; end
WHEN "100011010" => def_q_mem <= "00011010"; -- zig_zag8'd 29; end
WHEN "100011011" => def_q_mem <= "00011011"; -- zig_zag8'd 29; end
WHEN "100011100" => def_q_mem <= "00011101"; -- zig_zag8'd 34; end
WHEN "100011101" => def_q_mem <= "00100010"; -- zig_zag8'd 34; end
WHEN "100011110" => def_q_mem <= "00100101"; -- zig_zag8'd 34; end
WHEN "100011111" => def_q_mem <= "00101000"; -- zig_zag8'd 29; end
WHEN "100100000" => def_q_mem <= "00010110"; -- zig_zag8'd 29; end
WHEN "100100001" => def_q_mem <= "00011010"; -- zig_zag8'd 29; end
WHEN "100100010" => def_q_mem <= "00011011"; -- zig_zag8'd 27; end
WHEN "100100011" => def_q_mem <= "00011101"; -- zig_zag8'd 27; end
WHEN "100100100" => def_q_mem <= "00100000"; -- zig_zag8'd 29; end
WHEN "100100101" => def_q_mem <= "00100011"; -- zig_zag8'd 29; end
WHEN "100100110" => def_q_mem <= "00101000"; -- zig_zag8'd 32; end
WHEN "100100111" => def_q_mem <= "00110000"; -- zig_zag8'd 32; end
WHEN "100101000" => def_q_mem <= "00011010"; -- zig_zag8'd 34; end
WHEN "100101001" => def_q_mem <= "00011011"; -- zig_zag8'd 34; end
WHEN "100101010" => def_q_mem <= "00011101"; -- zig_zag8'd 37; end
WHEN "100101011" => def_q_mem <= "00100000"; -- zig_zag8'd 38; end
WHEN "100101100" => def_q_mem <= "00100011"; -- zig_zag8'd 37; end
WHEN "100101101" => def_q_mem <= "00101000"; -- zig_zag8'd 35; end
WHEN "100101110" => def_q_mem <= "00110000"; -- zig_zag8'd 35; end
WHEN "100101111" => def_q_mem <= "00111010"; -- zig_zag8'd 34; end
WHEN "100110000" => def_q_mem <= "00011010"; -- zig_zag8'd 35; end
WHEN "100110001" => def_q_mem <= "00011011"; -- zig_zag8'd 38; end
WHEN "100110010" => def_q_mem <= "00011101"; -- zig_zag8'd 38; end
WHEN "100110011" => def_q_mem <= "00100010"; -- zig_zag8'd 40; end
WHEN "100110100" => def_q_mem <= "00100110"; -- zig_zag8'd 40; end
WHEN "100110101" => def_q_mem <= "00101110"; -- zig_zag8'd 40; end
WHEN "100110110" => def_q_mem <= "00111000"; -- zig_zag8'd 48; end
WHEN "100110111" => def_q_mem <= "01000101"; -- zig_zag8'd 48; end
WHEN "100111000" => def_q_mem <= "00011011"; -- zig_zag8'd 46; end
WHEN "100111001" => def_q_mem <= "00011101"; -- zig_zag8'd 46; end
WHEN "100111010" => def_q_mem <= "00100011"; -- zig_zag8'd 56; end
WHEN "100111011" => def_q_mem <= "00100110"; -- zig_zag8'd 56; end
WHEN "100111100" => def_q_mem <= "00101110"; -- zig_zag8'd 58; end
WHEN "100111101" => def_q_mem <= "00111000"; -- zig_zag8'd 69; end
WHEN "100111110" => def_q_mem <= "01000101"; -- zig_zag8'd 69; end
WHEN "100111111" => def_q_mem <= "01010011"; -- zig_zag8'd 83; end
WHEN "11-------" => def_q_mem <= "00010000";
WHEN OTHERS => def_q_mem <= "00000000";
END CASE;
END IF;
END PROCESS;
--***************************************************************************
-- register def_q_mem . This is done to match the pipeline stage with that of
-- register def_q_mem . This is done to match the pipeline stage with that of
-- qscale code and the user defined Q matrix which has 2 pipe stages before the first
-- multiplier : pipe2
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
def_q_mem_reg <= "00000000";
def_q_mem_reg1 <= "00000000";
ELSIF (CLK'EVENT AND CLK = '1') THEN
def_q_mem_reg <= def_q_mem;
def_q_mem_reg1 <= def_q_mem_reg;
END IF;
END PROCESS;
--***************************************************************************
-- Two 64x8 memories to store the user defined intra and non-intra Qmatrix (q_value_new). A 68x12 memory is used to store the input quantized dct values
-- read in new intra Q value: pipe1
P_ram1: PROCESS (RST,CLK)
BEGIN
IF (RST = '1') THEN
q_value_new_intra(64 downto 1) <= (OTHERS => "00000000");
ELSIF (rising_edge (CLK)) THEN
IF (rdy_in = '1' AND load_intra_qmatrix_reg1 = '1' ) THEN
q_value_new_intra(CONV_INTEGER (cnt64)) <= q_value;
END IF;
END IF;
END PROCESS P_ram1;
P_ram2: PROCESS (RST,CLK)
BEGIN
IF (RST = '1') THEN
q_value_new_non_intra(64 downto 1) <= (OTHERS => "00000000");
ELSIF (rising_edge (CLK)) THEN
IF (rdy_in = '1' AND load_non_intra_qmatrix_reg1 = '1') THEN
q_value_new_non_intra(CONV_INTEGER (cnt64)) <= q_value;
END IF;
END IF;
END PROCESS P_ram2;
-- user defined Q values are read out :pipe2
P_ramout: PROCESS (RST,CLK)
BEGIN
IF (RST = '1') THEN
q_value_new_out <= (OTHERS => '0');
ELSIF (rising_edge (CLK)) THEN
IF (rdy_in = '1' AND macroblock_type_reg1 = '0') THEN
q_value_new_out <= q_value_new_intra(CONV_INTEGER (cnt64b));
ELSIF (rdy_in = '1' AND macroblock_type_reg1 = '1') THEN
q_value_new_out <= q_value_new_non_intra(CONV_INTEGER (cnt64b));
ELSE
q_value_new_out <= (OTHERS => '0');
END IF;
END IF;
END PROCESS P_ramout;
-- END MEMORY SECTION
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
qdct_in_reg <= "000000000000";
qdct_out <= "000000000000";
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (rdy_in = '1') THEN
qdct_in_reg <= quant_dct_in;
qdct_out <= qdct_in_reg;
END IF;
END IF;
END PROCESS;
--***************************************************************************
-- (2*quantised input + k). Multiplication by 2 is done by left shifting quant_in .
-- (2*quantised input + k). Multiplication by 2 is done by left shifting quant_in .
-- dct_out comp is active after 3 clocks. To match the pipe stage of dct_out_comp
-- with macroblock_type and dct_out, macroblock_type is registered for 3 clks and
-- dct_out for 1 clk.
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
qdct_out_comp <= '0';
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (qdct_out = "000000000000") THEN
qdct_out_comp <= '1';
ELSE
qdct_out_comp <= '0';
END IF;
END IF;
END PROCESS;
temp4 <= ( not(qdct_out(10 DOWNTO 0) + '1')) WHEN qdct_out(11) = '1' ELSE
qdct_out(10 DOWNTO 0);
--***************************************************************************
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
qdct_out_reg <= "000000000000";
qdct_out_mag2 <= '0';
qdct_out_mag3 <= '0';
qdct_out_mag4 <= '0';
qdct_out_mag5 <= '0';
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