📄 quant_vhd.vhd
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WHEN "001101100" => memoryQ <= "00000001001";
WHEN "001101101" => memoryQ <= "00000001001";
WHEN "001101110" => memoryQ <= "00000001001";
WHEN "001101111" => memoryQ <= "00000001001";
WHEN "001110000" => memoryQ <= "00000001001";
WHEN "001110001" => memoryQ <= "00000001001";
WHEN "001110010" => memoryQ <= "00000001001";
WHEN "001110011" => memoryQ <= "00000001000";
WHEN "001110100" => memoryQ <= "00000001000";
WHEN "001110101" => memoryQ <= "00000001000";
WHEN "001110110" => memoryQ <= "00000001000";
WHEN "001110111" => memoryQ <= "00000001000";
WHEN "001111000" => memoryQ <= "00000001000";
WHEN "001111001" => memoryQ <= "00000001000";
WHEN "001111010" => memoryQ <= "00000001000";
WHEN "001111011" => memoryQ <= "00000001000";
WHEN "001111100" => memoryQ <= "00000001000";
WHEN "001111101" => memoryQ <= "00000001000";
WHEN "001111110" => memoryQ <= "00000001000";
WHEN "001111111" => memoryQ <= "00000001000";
WHEN "010000000" => memoryQ <= "00000001000";
------------------------------------------------------------------------------
WHEN "010000001" => memoryQ <= "00000000111";
WHEN "010000010" => memoryQ <= "00000000111";
WHEN "010000011" => memoryQ <= "00000000111";
WHEN "010000100" => memoryQ <= "00000000111";
WHEN "010000101" => memoryQ <= "00000000111";
WHEN "010000110" => memoryQ <= "00000000111";
WHEN "010000111" => memoryQ <= "00000000111";
WHEN "010001000" => memoryQ <= "00000000111";
WHEN "010001001" => memoryQ <= "00000000111";
WHEN "010001010" => memoryQ <= "00000000111";
WHEN "010001011" => memoryQ <= "00000000111";
WHEN "010001100" => memoryQ <= "00000000111";
WHEN "010001101" => memoryQ <= "00000000111";
WHEN "010001110" => memoryQ <= "00000000111";
WHEN "010001111" => memoryQ <= "00000000111";
WHEN "010010000" => memoryQ <= "00000000111";
WHEN "010010001" => memoryQ <= "00000000111";
WHEN "010010010" => memoryQ <= "00000000111";
------------------------------------------------------------------------------
WHEN "010010011" => memoryQ <= "00000000110";
WHEN "010010100" => memoryQ <= "00000000110";
WHEN "010010101" => memoryQ <= "00000000110";
WHEN "010010110" => memoryQ <= "00000000110";
WHEN "010010111" => memoryQ <= "00000000110";
WHEN "010011000" => memoryQ <= "00000000110";
WHEN "010011001" => memoryQ <= "00000000110";
WHEN "010011010" => memoryQ <= "00000000110";
WHEN "010011011" => memoryQ <= "00000000110";
WHEN "010011100" => memoryQ <= "00000000110";
WHEN "010011101" => memoryQ <= "00000000110";
WHEN "010011110" => memoryQ <= "00000000110";
WHEN "010011111" => memoryQ <= "00000000110";
WHEN "010100000" => memoryQ <= "00000000110";
WHEN "010100001" => memoryQ <= "00000000110";
WHEN "010100010" => memoryQ <= "00000000110";
WHEN "010100011" => memoryQ <= "00000000110";
WHEN "010100100" => memoryQ <= "00000000110";
WHEN "010100101" => memoryQ <= "00000000110";
WHEN "010100110" => memoryQ <= "00000000110";
WHEN "010100111" => memoryQ <= "00000000110";
WHEN "010101000" => memoryQ <= "00000000110";
WHEN "010101001" => memoryQ <= "00000000110";
WHEN "010101010" => memoryQ <= "00000000110";
WHEN "010101011" => memoryQ <= "00000000110";
WHEN "010101100" => memoryQ <= "00000000101";
------------------------------------------------------------------------------
WHEN "010101101" => memoryQ <= "00000000101";
WHEN "010101110" => memoryQ <= "00000000101";
WHEN "010101111" => memoryQ <= "00000000101";
WHEN "010110000" => memoryQ <= "00000000101";
WHEN "010110001" => memoryQ <= "00000000101";
WHEN "010110010" => memoryQ <= "00000000101";
WHEN "010110011" => memoryQ <= "00000000101";
WHEN "010110100" => memoryQ <= "00000000101";
WHEN "010110101" => memoryQ <= "00000000101";
WHEN "010110110" => memoryQ <= "00000000101";
WHEN "010110111" => memoryQ <= "00000000101";
WHEN "010111000" => memoryQ <= "00000000101";
WHEN "010111001" => memoryQ <= "00000000101";
WHEN "010111010" => memoryQ <= "00000000101";
WHEN "010111011" => memoryQ <= "00000000101";
WHEN "010111100" => memoryQ <= "00000000101";
WHEN "010111101" => memoryQ <= "00000000101";
WHEN "010111110" => memoryQ <= "00000000101";
WHEN "010111111" => memoryQ <= "00000000101";
WHEN "011000000" => memoryQ <= "00000000101";
WHEN "011000001" => memoryQ <= "00000000101";
WHEN "011000010" => memoryQ <= "00000000101";
WHEN "011000011" => memoryQ <= "00000000101";
WHEN "011000100" => memoryQ <= "00000000101";
WHEN "011000101" => memoryQ <= "00000000101";
WHEN "011000110" => memoryQ <= "00000000101";
WHEN "011000111" => memoryQ <= "00000000101";
WHEN "011001000" => memoryQ <= "00000000101";
WHEN "011001001" => memoryQ <= "00000000101";
WHEN "011001010" => memoryQ <= "00000000101";
WHEN "011001011" => memoryQ <= "00000000101";
WHEN "011001100" => memoryQ <= "00000000101";
WHEN "011001101" => memoryQ <= "00000000101";
WHEN "011001110" => memoryQ <= "00000000101";
------------------------------------------------------------------------------
WHEN "011001111" => memoryQ <= "00000000100";
WHEN "011010000" => memoryQ <= "00000000100";
WHEN "011010001" => memoryQ <= "00000000100";
WHEN "011010010" => memoryQ <= "00000000100";
WHEN "011010011" => memoryQ <= "00000000100";
WHEN "011010100" => memoryQ <= "00000000100";
WHEN "011010101" => memoryQ <= "00000000100";
WHEN "011010110" => memoryQ <= "00000000100";
WHEN "011010111" => memoryQ <= "00000000100";
WHEN "011011000" => memoryQ <= "00000000100";
WHEN "011011001" => memoryQ <= "00000000100";
WHEN "011011010" => memoryQ <= "00000000100";
WHEN "011011011" => memoryQ <= "00000000100";
WHEN "011011100" => memoryQ <= "00000000100";
WHEN "011011101" => memoryQ <= "00000000100";
WHEN "011011110" => memoryQ <= "00000000100";
WHEN "011011111" => memoryQ <= "00000000100";
WHEN "011100000" => memoryQ <= "00000000100";
WHEN "011100001" => memoryQ <= "00000000100";
WHEN "011100010" => memoryQ <= "00000000100";
WHEN "011100011" => memoryQ <= "00000000100";
WHEN "011100100" => memoryQ <= "00000000100";
WHEN "011100101" => memoryQ <= "00000000100";
WHEN "011100110" => memoryQ <= "00000000100";
WHEN "011100111" => memoryQ <= "00000000100";
WHEN "011101000" => memoryQ <= "00000000100";
WHEN "011101001" => memoryQ <= "00000000100";
WHEN "011101010" => memoryQ <= "00000000100";
WHEN "011101011" => memoryQ <= "00000000100";
WHEN "011101100" => memoryQ <= "00000000100";
WHEN "011101101" => memoryQ <= "00000000100";
WHEN "011101110" => memoryQ <= "00000000100";
WHEN "011101111" => memoryQ <= "00000000100";
WHEN "011110000" => memoryQ <= "00000000100";
WHEN "011110001" => memoryQ <= "00000000100";
WHEN "011110010" => memoryQ <= "00000000100";
WHEN "011110011" => memoryQ <= "00000000100";
WHEN "011110100" => memoryQ <= "00000000100";
WHEN "011110101" => memoryQ <= "00000000100";
WHEN "011110110" => memoryQ <= "00000000100";
WHEN "011110111" => memoryQ <= "00000000100";
WHEN "011111000" => memoryQ <= "00000000100";
WHEN "011111001" => memoryQ <= "00000000100";
WHEN "011111010" => memoryQ <= "00000000100";
WHEN "011111011" => memoryQ <= "00000000100";
WHEN "011111100" => memoryQ <= "00000000100";
WHEN "011111101" => memoryQ <= "00000000100";
WHEN "011111110" => memoryQ <= "00000000100";
WHEN "011111111" => memoryQ <= "00000000100";
WHEN "100000000" => memoryQ <= "00000000100";
WHEN OTHERS => memoryQ <= "00000000000";
END CASE;
END IF;
END PROCESS;
--***************************************************************************
-- [(1/Qmatrix)*(16/qscale)] => 11bits(1 + 10 decimal) * 13bits(5.8) = 24bits
-- [(1/Qmatrix)*(16/qscale)] => 11bits(1 + 10 decimal) * 13bits(5.8) = 24bits
-- (last 18 bits being decimal plus 5 msb). Rounding off is done here and of the
-- 24 bits only 17 msbs are used(ie., 6 + 11 decimal). This will also enable the
-- use of the multiplier in Virtex2 devices. Inputs to prod1 has 4 pipe stages each.
-- Prod1 valid after 5 clk. (4 pipe stages before mult. plus 1 pipe after mult)
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
prod1 <= (OTHERS => '0');
prod1_reg <= (OTHERS => '0');
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (rdy_in = '1') THEN
prod1 <= (memoryQ * qscale_reg1);
ELSE
END IF;
END IF;
END PROCESS;
--***************************************************************************
-- prod1 (17 bits with 6.11 decimal bits)
-- prod1 (17 bits with 6.11 decimal bits)
-- dct_out_reg (12 bits) = 17 bits. Input data is 12 bits with 1 sign and 11 data
-- bits, sign extended to 17. So out of these 17 bits, only the 11 lsbs are
-- real data, the 6 msbs are sign information.
-- prod2 = 17bits + 17 bits (6 + 11 decimal) = 34 bits. Of this, 11 lsbs are decimal and
-- 6 msbs are sign extensions. The valid output would be [27:11] = 16 bits
-- after 6 clks
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
prod2 <= (OTHERS => '0');
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (rdy_in = '1') THEN
prod2 <= (dct_in_pipe5 * prod1(23 DOWNTO 7)); -- 27 bits, with 12 decimal
ELSE
END IF;
END IF;
END PROCESS;
temp6 <= (prod2(27 DOWNTO 9) - "0000000000000000010") WHEN
dct_in_pipe6_sign = '1' ELSE (prod2(27 DOWNTO 9) +
"0000000000000000010");
--***************************************************************************
-- compare sign magnitude of input DCT values. To match the pipeline,
-- compare sign magnitude of input DCT values. To match the pipeline,
-- dct_out_reg should be registered once more . The section is used to calculate
-- k/2. k/2 = 0 for '0' dct input, k/2 = .5 for +ve dct input and k/2 = -.5
-- for -ve dct input. For intra block, macroblock type = 1'b0 and k = '0'.
-- Prod2 has 6 pipe stages. Prod2_k occurs at the 7th clk
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
prod2_k <= (OTHERS => '0');
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (rdy_in = '1' AND macroblock_type_pipe6 = '1') THEN
IF (dct_in_pipe6 = "00000000000") THEN
prod2_k <= prod2(27 DOWNTO 9); -- 2 decimal places
ELSE
prod2_k <= temp6;
END IF;
ELSE
IF (rdy_in = '1' AND macroblock_type_pipe6 = '0') THEN
prod2_k <= prod2(27 DOWNTO 9); -- 2 decimal places
END IF;
END IF;
END IF;
END PROCESS;
temp7 <= (prod2_k(18 DOWNTO 2) + "00000000000000001") WHEN
prod2_k(1) = '1' ELSE prod2_k(18 DOWNTO 2);
prod2_round <= temp7 ;
temp8 <= ( not(prod2_round(11 DOWNTO 0)) + 1) WHEN (dct_in_pipe7_sign) =
'1' ELSE (prod2_round(11 DOWNTO 0));
--***************************************************************************
-- sign correction. prod2_round has 6 clk stages
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
quant_dct_out <= "000000000000";
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (rdy_in = '1') THEN
quant_dct_out <= temp8;
END IF;
END IF;
END PROCESS;
--***************************************************************************
-- Ist valid ouput occurs after 6 clks
PROCESS (CLK, RST)
BEGIN
IF (RST = '1') THEN
quant_rdy_out <= '0';
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (cnt6 = "0111") THEN
quant_rdy_out <= '1';
END IF;
END IF;
END PROCESS;
END translated;
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