iquant_v.v

IDCT - xlinix design in vhdl

        7'b1001100 : begin q_scale_mem <= 10'b0011000000; end 
        7'b1001101 : begin q_scale_mem <= 10'b0011010000; end   
        7'b1001110 : begin q_scale_mem <= 10'b0011100000; end 
        7'b1001111 : begin q_scale_mem <= 10'b0011110000; end    
        7'b1010000 : begin q_scale_mem <= 10'b0100000000; end 
        7'b1010001 : begin q_scale_mem <= 10'b0100010000; end     
        7'b1010010 : begin q_scale_mem <= 10'b0100100000; end 
        7'b1010011 : begin q_scale_mem <= 10'b0100110000; end     
        7'b1010100 : begin q_scale_mem <= 10'b0101000000; end 
        7'b1010101 : begin q_scale_mem <= 10'b0101010000; end     
        7'b1010110 : begin q_scale_mem <= 10'b0101100000; end 
        7'b1010111 : begin q_scale_mem <= 10'b0101110000; end    
        7'b1011000 : begin q_scale_mem <= 10'b0110000000; end 
        7'b1011001 : begin q_scale_mem <= 10'b0110010000; end    
        7'b1011010 : begin q_scale_mem <= 10'b0110100000; end 
        7'b1011011 : begin q_scale_mem <= 10'b0110110000; end    
        7'b1011100 : begin q_scale_mem <= 10'b0111000000; end 
        7'b1011101 : begin q_scale_mem <= 10'b0111010000; end   
        7'b1011110 : begin q_scale_mem <= 10'b0111100000; end 

        7'b1100001 : begin q_scale_mem <= 10'b0000001000; end /* .03125 */    
        7'b1100010 : begin q_scale_mem <= 10'b0000010000; end /* .0625  */
        7'b1100011 : begin q_scale_mem <= 10'b0000011000; end /* .09375 */    
        7'b1100100 : begin q_scale_mem <= 10'b0000100000; end /* .125   */
        7'b1100101 : begin q_scale_mem <= 10'b0000101000; end /* .15625 */    
        7'b1100110 : begin q_scale_mem <= 10'b0000110000; end /* .1875  */
        7'b1100111 : begin q_scale_mem <= 10'b0000111000; end /* .21875 */   
        7'b1101000 : begin q_scale_mem <= 10'b0001000000; end /* .25    */
        7'b1101001 : begin q_scale_mem <= 10'b0001010000; end /* .3125  */   
        7'b1101010 : begin q_scale_mem <= 10'b0001100000; end /* .375   */
        7'b1101011 : begin q_scale_mem <= 10'b0001110000; end /* .4375  */   
        7'b1101100 : begin q_scale_mem <= 10'b0010000000; end /* .5     */
        7'b1101101 : begin q_scale_mem <= 10'b0010010000; end /* .5625  */  
        7'b1101110 : begin q_scale_mem <= 10'b0010100000; end /* .625   */
        7'b1101111 : begin q_scale_mem <= 10'b0010110000; end /* .6875  */   
        7'b1110000 : begin q_scale_mem <= 10'b0011000000; end /* .75    */
        7'b1110001 : begin q_scale_mem <= 10'b0011100000; end /* .875   */   
        7'b1110010 : begin q_scale_mem <= 10'b0100000000; end /* 1      */
        7'b1110011 : begin q_scale_mem <= 10'b0100100000; end /* 1.125  */   
        7'b1110100 : begin q_scale_mem <= 10'b0101000000; end /* 1.25   */
        7'b1110101 : begin q_scale_mem <= 10'b0101100000; end /* 1.375  */   
        7'b1110110 : begin q_scale_mem <= 10'b0110000000; end /* 1.5    */
        7'b1110111 : begin q_scale_mem <= 10'b0110100000; end /* 1.625  */   
        7'b1111000 : begin q_scale_mem <= 10'b0111000000; end /* 1.75   */
        7'b1111001 : begin q_scale_mem <= 10'b1000000000; end /* 2      */   
        7'b1111010 : begin q_scale_mem <= 10'b1001000000; end /* 2.25   */
        7'b1111011 : begin q_scale_mem <= 10'b1010000000; end /* 2.5    */   
        7'b1111100 : begin q_scale_mem <= 10'b1011000000; end /* 2.75   */
        7'b1111101 : begin q_scale_mem <= 10'b1100000000; end /* 3      */   
        7'b1111110 : begin q_scale_mem <= 10'b1101000000; end /* 3.25   */
        7'b1111111 : begin q_scale_mem <= 10'b1110000000; end /* 3.5    */
		default: begin q_scale_mem <= 10'b0000000000; end
        endcase
end

/*****************************************************************************/

/* register qscale for 64 clks. This is done to make sure that all the 64 
   DCT coefficients see the same qscale: pipe2 */

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       qscale_reg <= 10'b0;
   else 
       qscale_reg <= q_scale_mem;
   end

/*****************************************************************************/

assign def_qmem_sel = {cnt_start,macroblock_type_reg1,cnt64b};
/* Two 64x8 memories to store the default intra and non-intra Qmatrix (q_value_def) . 
Values are NOT stored in zig-zag order: pipe1 */
always @ (posedge CLK)
   //begin
   //if (RST)
   //    begin
   //      def_q_mem <= 8'd0; 
   //    end
   //else if (cnt_start == 1'b1 && macroblock_type_reg1 == 1'b0 )
       begin
	   casex (def_qmem_sel) //(cnt64b)
        9'b101000000 :   def_q_mem <= 8'd8;   //zig_zag 8'd 8;  end     
        9'b100000001 :   def_q_mem <= 8'd16;  //zig_zag8'd 16; end 
        9'b100000010 :   def_q_mem <= 8'd19;  //zig_zag8'd 16; end     
        9'b100000011 :   def_q_mem <= 8'd22;  //zig_zag8'd 19; end 
        9'b100000100 :   def_q_mem <= 8'd26;  //zig_zag8'd 16; end     
        9'b100000101 :   def_q_mem <= 8'd27;  //zig_zag8'd 19; end 
        9'b100000110 :   def_q_mem <= 8'd29;  //zig_zag8'd 22; end    
        9'b100000111 :   def_q_mem <= 8'd34;  //zig_zag8'd 22; end 
        9'b100001000 :   def_q_mem <= 8'd16;  //zig_zag8'd 22; end    
        9'b100001001 :   def_q_mem <= 8'd16;  //zig_zag8'd 22; end 
        9'b100001010 :   def_q_mem <= 8'd22;  //zig_zag8'd 22; end    
        9'b100001011 :   def_q_mem <= 8'd24;  //zig_zag8'd 22; end 
        9'b100001100 :   def_q_mem <= 8'd27;  //zig_zag8'd 26; end   
        9'b100001101 :   def_q_mem <= 8'd29;  //zig_zag8'd 24; end 
        9'b100001110 :   def_q_mem <= 8'd34;  //zig_zag8'd 26; end    
        9'b100001111 :   def_q_mem <= 8'd37;  //zig_zag8'd 27; end 
        9'b100010000 :   def_q_mem <= 8'd19;  //zig_zag8'd 27; end     
        9'b100010001 :   def_q_mem <= 8'd22;  //zig_zag8'd 27; end 
        9'b100010010 :   def_q_mem <= 8'd26;  //zig_zag8'd 26; end     
        9'b100010011 :   def_q_mem <= 8'd27;  //zig_zag8'd 26; end 
        9'b100010100 :   def_q_mem <= 8'd29;  //zig_zag8'd 26; end     
        9'b100010101 :   def_q_mem <= 8'd34;  //zig_zag8'd 26; end 
        9'b100010110 :   def_q_mem <= 8'd34;  //zig_zag8'd 27; end    
        9'b100010111 :   def_q_mem <= 8'd38;  //zig_zag8'd 27; end 
        9'b100011000 :   def_q_mem <= 8'd22;  //zig_zag8'd 27; end    
        9'b100011001 :   def_q_mem <= 8'd22;  //zig_zag8'd 29; end 
        9'b100011010 :   def_q_mem <= 8'd26;  //zig_zag8'd 29; end    
        9'b100011011 :   def_q_mem <= 8'd27;  //zig_zag8'd 29; end 
        9'b100011100 :   def_q_mem <= 8'd29;  //zig_zag8'd 34; end   
        9'b100011101 :   def_q_mem <= 8'd34;  //zig_zag8'd 34; end 
        9'b100011110 :   def_q_mem <= 8'd37;  //zig_zag8'd 34; end    
        9'b100011111 :   def_q_mem <= 8'd40;  //zig_zag8'd 29; end 
        9'b100100000 :   def_q_mem <= 8'd22;  //zig_zag8'd 29; end   
        9'b100100001 :   def_q_mem <= 8'd26;  //zig_zag8'd 29; end 
        9'b100100010 :   def_q_mem <= 8'd27;  //zig_zag8'd 27; end    
        9'b100100011 :   def_q_mem <= 8'd29;  //zig_zag8'd 27; end 
        9'b100100100 :   def_q_mem <= 8'd32;  //zig_zag8'd 29; end     
        9'b100100101 :   def_q_mem <= 8'd35;  //zig_zag8'd 29; end 
        9'b100100110 :   def_q_mem <= 8'd40;  //zig_zag8'd 32; end     
        9'b100100111 :   def_q_mem <= 8'd48;  //zig_zag8'd 32; end 
        9'b100101000 :   def_q_mem <= 8'd26;  //zig_zag8'd 34; end     
        9'b100101001 :   def_q_mem <= 8'd27;  //zig_zag8'd 34; end 
        9'b100101010 :   def_q_mem <= 8'd29;  //zig_zag8'd 37; end    
        9'b100101011 :   def_q_mem <= 8'd32;  //zig_zag8'd 38; end 
        9'b100101100 :   def_q_mem <= 8'd35;  //zig_zag8'd 37; end    
        9'b100101101 :   def_q_mem <= 8'd40;  //zig_zag8'd 35; end 
        9'b100101110 :   def_q_mem <= 8'd48;  //zig_zag8'd 35; end    
        9'b100101111 :   def_q_mem <= 8'd58;  //zig_zag8'd 34; end 
        9'b100110000 :   def_q_mem <= 8'd26;  //zig_zag8'd 35; end   
        9'b100110001 :   def_q_mem <= 8'd27;  //zig_zag8'd 38; end 
        9'b100110010 :   def_q_mem <= 8'd29;  //zig_zag8'd 38; end    
        9'b100110011 :   def_q_mem <= 8'd34;  //zig_zag8'd 40; end 
        9'b100110100 :   def_q_mem <= 8'd38;  //zig_zag8'd 40; end   
        9'b100110101 :   def_q_mem <= 8'd46;  //zig_zag8'd 40; end 
        9'b100110110 :   def_q_mem <= 8'd56;  //zig_zag8'd 48; end    
        9'b100110111 :   def_q_mem <= 8'd69;  //zig_zag8'd 48; end 
        9'b100111000 :   def_q_mem <= 8'd27;  //zig_zag8'd 46; end     
        9'b100111001 :   def_q_mem <= 8'd29;  //zig_zag8'd 46; end 
        9'b100111010 :   def_q_mem <= 8'd35;  //zig_zag8'd 56; end     
        9'b100111011 :   def_q_mem <= 8'd38;  //zig_zag8'd 56; end 
        9'b100111100 :   def_q_mem <= 8'd46;  //zig_zag8'd 58; end     
        9'b100111101 :   def_q_mem <= 8'd56;  //zig_zag8'd 69; end 
        9'b100111110 :   def_q_mem <= 8'd69;  //zig_zag8'd 69; end    
        9'b100111111 :   def_q_mem <= 8'd83;  //zig_zag8'd 83; end 
        9'b11xxxxxxx :   def_q_mem <= 8'd16;  
        default: def_q_mem <= 8'd0;
		endcase
  end

  /*****************************************************************************/

/* register def_q_mem . This is done to match the pipeline stage with that of 
 qscale code and the user defined Q matrix which has 2 pipe stages before the first
 multiplier : pipe2*/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
       def_q_mem_reg <= 8'b0; def_q_mem_reg1 <= 8'b0;
       end
   else 
       begin
       def_q_mem_reg <= def_q_mem;
       def_q_mem_reg1 <= def_q_mem_reg;
       end
   end
/*****************************************************************************/

/* Two 64x8 memories to store the user defined intra and non-intra Qmatrix (q_value_new). A 68x12 memory is used to store the input quantized dct values */

initial
begin
q_value_new_intra[0] <= 8'b0; q_value_new_intra[1] <= 8'b0; 
q_value_new_intra[2] <= 8'b0; q_value_new_intra[3] <= 8'b0; 
q_value_new_intra[4] <= 8'b0; q_value_new_intra[5] <= 8'b0; 
q_value_new_intra[6] <= 8'b0; q_value_new_intra[7] <= 8'b0; 
q_value_new_intra[8] <= 8'b0; q_value_new_intra[9] <= 8'b0; 
q_value_new_intra[10] <= 8'b0; q_value_new_intra[11] <= 8'b0; 
q_value_new_intra[12] <= 8'b0; q_value_new_intra[13] <= 8'b0; 
q_value_new_intra[14] <= 8'b0; q_value_new_intra[15] <= 8'b0; 
q_value_new_intra[16] <= 8'b0; q_value_new_intra[17] <= 8'b0; 
q_value_new_intra[18] <= 8'b0; q_value_new_intra[19] <= 8'b0; 
q_value_new_intra[20] <= 8'b0; q_value_new_intra[21] <= 8'b0; 
q_value_new_intra[22] <= 8'b0; q_value_new_intra[23] <= 8'b0; 
q_value_new_intra[24] <= 8'b0; q_value_new_intra[25] <= 8'b0; 
q_value_new_intra[26] <= 8'b0; q_value_new_intra[27] <= 8'b0; 
q_value_new_intra[28] <= 8'b0; q_value_new_intra[29] <= 8'b0;
q_value_new_intra[30] <= 8'b0; q_value_new_intra[31] <= 8'b0; 
q_value_new_intra[32] <= 8'b0; q_value_new_intra[33] <= 8'b0; 
q_value_new_intra[34] <= 8'b0; q_value_new_intra[35] <= 8'b0; 
q_value_new_intra[36] <= 8'b0; q_value_new_intra[37] <= 8'b0; 
q_value_new_intra[38] <= 8'b0; q_value_new_intra[39] <= 8'b0; 
q_value_new_intra[40] <= 8'b0; q_value_new_intra[41] <= 8'b0; 
q_value_new_intra[42] <= 8'b0; q_value_new_intra[43] <= 8'b0; 
q_value_new_intra[44] <= 8'b0; q_value_new_intra[45] <= 8'b0; 
q_value_new_intra[46] <= 8'b0; q_value_new_intra[47] <= 8'b0; 
q_value_new_intra[48] <= 8'b0; q_value_new_intra[49] <= 8'b0; 
q_value_new_intra[50] <= 8'b0; q_value_new_intra[51] <= 8'b0; 
q_value_new_intra[52] <= 8'b0; q_value_new_intra[53] <= 8'b0; 
q_value_new_intra[54] <= 8'b0; q_value_new_intra[55] <= 8'b0; 
q_value_new_intra[56] <= 8'b0; q_value_new_intra[57] <= 8'b0; 
q_value_new_intra[58] <= 8'b0; q_value_new_intra[59] <= 8'b0;
q_value_new_intra[60] <= 8'b0; q_value_new_intra[61] <= 8'b0; 
q_value_new_intra[62] <= 8'b0; q_value_new_intra[63] <= 8'b0;
q_value_new_intra[64] <= 8'b0;
q_value_new_non_intra[0] <= 8'b0; q_value_new_non_intra[1] <= 8'b0; 
q_value_new_non_intra[2] <= 8'b0; q_value_new_non_intra[3] <= 8'b0; 
q_value_new_non_intra[4] <= 8'b0; q_value_new_non_intra[5] <= 8'b0; 
q_value_new_non_intra[6] <= 8'b0; q_value_new_non_intra[7] <= 8'b0; 
q_value_new_non_intra[8] <= 8'b0; q_value_new_non_intra[9] <= 8'b0; 
q_value_new_non_intra[10] <= 8'b0; q_value_new_non_intra[11] <= 8'b0; 
q_value_new_non_intra[12] <= 8'b0; q_value_new_non_intra[13] <= 8'b0; 
q_value_new_non_intra[14] <= 8'b0; q_value_new_non_intra[15] <= 8'b0; 
q_value_new_non_intra[16] <= 8'b0; q_value_new_non_intra[17] <= 8'b0; 
q_value_new_non_intra[18] <= 8'b0; q_value_new_non_intra[19] <= 8'b0; 
q_value_new_non_intra[20] <= 8'b0; q_value_new_non_intra[21] <= 8'b0; 
q_value_new_non_intra[22] <= 8'b0; q_value_new_non_intra[23] <= 8'b0; 
q_value_new_non_intra[24] <= 8'b0; q_value_new_non_intra[25] <= 8'b0; 
q_value_new_non_intra[26] <= 8'b0; q_value_new_non_intra[27] <= 8'b0; 
q_value_new_non_intra[28] <= 8'b0; q_value_new_non_intra[29] <= 8'b0;
q_value_new_non_intra[30] <= 8'b0; q_value_new_non_intra[31] <= 8'b0; 
q_value_new_non_intra[32] <= 8'b0; q_value_new_non_intra[33] <= 8'b0; 
q_value_new_non_intra[34] <= 8'b0; q_value_new_non_intra[35] <= 8'b0; 
q_value_new_non_intra[36] <= 8'b0; q_value_new_non_intra[37] <= 8'b0; 
q_value_new_non_intra[38] <= 8'b0; q_value_new_non_intra[39] <= 8'b0; 
q_value_new_non_intra[40] <= 8'b0; q_value_new_non_intra[41] <= 8'b0; 
q_value_new_non_intra[42] <= 8'b0; q_value_new_non_intra[43] <= 8'b0; 
q_value_new_non_intra[44] <= 8'b0; q_value_new_non_intra[45] <= 8'b0; 
q_value_new_non_intra[46] <= 8'b0; q_value_new_non_intra[47] <= 8'b0; 
q_value_new_non_intra[48] <= 8'b0; q_value_new_non_intra[49] <= 8'b0;   
q_value_new_non_intra[50] <= 8'b0; q_value_new_non_intra[51] <= 8'b0; 
q_value_new_non_intra[52] <= 8'b0; q_value_new_non_intra[53] <= 8'b0;
q_value_new_non_intra[54] <= 8'b0; q_value_new_non_intra[55] <= 8'b0; 
q_value_new_non_intra[56] <= 8'b0; q_value_new_non_intra[57] <= 8'b0; 
q_value_new_non_intra[58] <= 8'b0; q_value_new_non_intra[59] <= 8'b0;   
q_value_new_non_intra[60] <= 8'b0; q_value_new_non_intra[61] <= 8'b0; 
q_value_new_non_intra[62] <= 8'b0; q_value_new_non_intra[63] <= 8'b0; 
q_value_new_non_intra[64] <= 8'b0;  
end

/* read in new intra Q value: pipe1 */
always @ (posedge CLK)
if (rdy_in == 1'b1 && load_intra_qmatrix_reg1 == 1'b1)
q_value_new_intra[cnt64]<= q_value;

/* read in new non intra Q values:pipe1 */
always @ (posedge CLK)
if (rdy_in == 1'b1 && load_non_intra_qmatrix_reg1 == 1'b1)
q_value_new_non_intra[cnt64] <= q_value;


/* user defined Q values are read out :pipe2*/
always @ (posedge CLK)
  begin
     if (rdy_in == 1'b1 && macroblock_type_reg1 == 1'b0)
       q_value_new_out <= q_value_new_intra[cnt64b];
     else if (rdy_in == 1'b1 && macroblock_type_reg1 == 1'b1)
       q_value_new_out <= q_value_new_non_intra[cnt64b];
     else q_value_new_out <= 8'b0;
  end


/* END MEMORY SECTION */

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
          qdct_in_reg <= 12'b0; qdct_out <= 12'b0; 
       end
   else if (rdy_in == 1'b1)
       begin
		     qdct_in_reg <= quant_dct_in;
          qdct_out <= qdct_in_reg;
		   end
   end
/*****************************************************************************/



/* (2*quantised input + k). Multiplication by 2 is done by left shifting quant_in .
dct_out comp is active after 3 clocks. To match the pipe stage of dct_out_comp
with macroblock_type and dct_out, macroblock_type is registered for 3 clks and
dct_out for 1 clk.*/

always @ (posedge CLK or posedge RST)
   begin
   if (RST)
       begin
          qdct_out_comp <= 1'b0; 
       end
   else 
       begin
         if (qdct_out == 12'b0)
            qdct_out_comp <= 1'b1;
         else
            qdct_out_comp <= 1'b0;
   	   end
   end
/*****************************************************************************/