mcbsp_xmit_master.c

DSP的MCBSP作为端口使用

/* To flag an interrupt to the CPU when EDMA transfer is done  */
/* Transfer completion interrupt 12 sets flag = 1 when set     */
#if (EDMA_SUPPORT)
  while (!xmit0_done);
#endif

MCBSP_close(hMcbsp0);  /* close McBSP port */

#if (DMA_SUPPORT)      /* close DMA channels */
DMA_close(hDma2);
#endif

#if (EDMA_SUPPPORT)
EDMA_close(hEdma1);    /* close EDMA channel */
EDMA_close(hEdmadummy);
#endif

} /* end main, program ends here */

/*--------------------------------------------------------------------------------*/
/* init_mcbsp0_master()                                                           */
/*--------------------------------------------------------------------------------*/
/* MCBSP Config structure */
/* Setup the MCBSP_0 for data transfer */
void
init_mcbsp0_master(void)
{  
MCBSP_Config mcbspCfg0 = {
#if (EDMA_SUPPORT)
    MCBSP_SPCR_RMK(
		   MCBSP_SPCR_FREE_DEFAULT,  /* All fields in SPCR set to default values */
		   MCBSP_SPCR_SOFT_DEFAULT,
           MCBSP_SPCR_FRST_DEFAULT,  
           MCBSP_SPCR_GRST_DEFAULT,
           MCBSP_SPCR_XINTM_DEFAULT,
           MCBSP_SPCR_XSYNCERR_DEFAULT,
           MCBSP_SPCR_XRST_DEFAULT,
           MCBSP_SPCR_DLB_DEFAULT,
           MCBSP_SPCR_RJUST_DEFAULT,
           MCBSP_SPCR_CLKSTP_DEFAULT,
           MCBSP_SPCR_DXENA_DEFAULT,
           MCBSP_SPCR_RINTM_DEFAULT,
           MCBSP_SPCR_RSYNCERR_DEFAULT,
           MCBSP_SPCR_RRST_DEFAULT
           ),
#endif
#if (DMA_SUPPORT)
   MCBSP_SPCR_RMK(  
          MCBSP_SPCR_FRST_DEFAULT,   /* All fields in SPCR set to default values */
          MCBSP_SPCR_GRST_DEFAULT,
          MCBSP_SPCR_XINTM_DEFAULT,
          MCBSP_SPCR_XSYNCERR_DEFAULT,
          MCBSP_SPCR_XRST_DEFAULT,
          MCBSP_SPCR_DLB_DEFAULT,
          MCBSP_SPCR_RJUST_DEFAULT,
          MCBSP_SPCR_CLKSTP_DEFAULT,
          MCBSP_SPCR_RINTM_DEFAULT,
          MCBSP_SPCR_RSYNCERR_DEFAULT,
          MCBSP_SPCR_RRST_DEFAULT
          ),
#endif
#if (EDMA_SUPPORT)
    MCBSP_RCR_RMK(
           MCBSP_RCR_RPHASE_DEFAULT,  /* All fields in RCR set to default values  */
           MCBSP_RCR_RFRLEN2_DEFAULT,
           MCBSP_RCR_RWDLEN2_DEFAULT,
           MCBSP_RCR_RCOMPAND_DEFAULT,
           MCBSP_RCR_RFIG_DEFAULT,
           MCBSP_RCR_RDATDLY_DEFAULT,
           MCBSP_RCR_RFRLEN1_DEFAULT,
           MCBSP_RCR_RWDLEN1_DEFAULT,
           MCBSP_RCR_RWDREVRS_DEFAULT
           ),
#endif
#if (DMA_SUPPORT)
    MCBSP_RCR_RMK(
           MCBSP_RCR_RPHASE_DEFAULT,  /* All fields in RCR set to default values  */
           MCBSP_RCR_RFRLEN2_DEFAULT,
           MCBSP_RCR_RWDLEN2_DEFAULT,
           MCBSP_RCR_RCOMPAND_DEFAULT,
           MCBSP_RCR_RFIG_DEFAULT,
           MCBSP_RCR_RDATDLY_DEFAULT,
           MCBSP_RCR_RFRLEN1_DEFAULT,
           MCBSP_RCR_RWDLEN1_DEFAULT
           ),
#endif
#if (EDMA_SUPPORT)
    MCBSP_XCR_RMK(
           MCBSP_XCR_XPHASE_SINGLE,   /* Single phase transmit frame */
           MCBSP_XCR_XFRLEN2_DEFAULT, 
           MCBSP_XCR_XWDLEN2_DEFAULT,
           MCBSP_XCR_XCOMPAND_DEFAULT,
           MCBSP_XCR_XFIG_DEFAULT,
           MCBSP_XCR_XDATDLY_1BIT,    /* 1-bit transmit data delay   */ 
           MCBSP_XCR_XFRLEN1_DEFAULT,
           MCBSP_XCR_XWDLEN1_DEFAULT,
           MCBSP_XCR_XWDREVRS_DEFAULT
           ),
#endif
#if (DMA_SUPPORT)
    MCBSP_XCR_RMK(
           MCBSP_XCR_XPHASE_SINGLE,   /* Single phase transmit frame */
           MCBSP_XCR_XFRLEN2_DEFAULT,
           MCBSP_XCR_XWDLEN2_DEFAULT,
           MCBSP_XCR_XCOMPAND_DEFAULT,
           MCBSP_XCR_XFIG_DEFAULT,
           MCBSP_XCR_XDATDLY_1BIT,    /* 1-bit transmit data delay   */ 
           MCBSP_XCR_XFRLEN1_DEFAULT,
           MCBSP_XCR_XWDLEN1_DEFAULT
           ),
#endif
     MCBSP_SRGR_RMK(
           MCBSP_SRGR_GSYNC_DEFAULT,
           MCBSP_SRGR_CLKSP_DEFAULT,
           MCBSP_SRGR_CLKSM_INTERNAL, /* Internal clock source               */ 
           MCBSP_SRGR_FSGM_FSG,       /* FSX driven by SRG frame sync signal */    
           MCBSP_SRGR_FPER_DEFAULT,
           MCBSP_SRGR_FWID_DEFAULT,
           MCBSP_SRGR_CLKGDV_OF(0x0) /* CLock divide of 1                   */
           ),
#if (C64_SUPPORT)
     MCBSP_MCR_RMK(                  /* only for 64x                               */
           MCBSP_MCR_XMCME_DEFAULT,  /* All fields in MCR set to default values    */
           MCBSP_MCR_XPBBLK_DEFAULT,
           MCBSP_MCR_XPABLK_DEFAULT,
           MCBSP_MCR_XMCM_DEFAULT,
           MCBSP_MCR_RPBBLK_DEFAULT,
           MCBSP_MCR_RMCME_DEFAULT,
           MCBSP_MCR_RPABLK_DEFAULT,
           MCBSP_MCR_RMCM_DEFAULT
           ),
#else
     MCBSP_MCR_RMK(
           MCBSP_MCR_XPBBLK_DEFAULT, /* All fields in MCR set to default values    */
           MCBSP_MCR_XPABLK_DEFAULT,
           MCBSP_MCR_XMCM_DEFAULT,
           MCBSP_MCR_RPBBLK_DEFAULT,
           MCBSP_MCR_RPABLK_DEFAULT,
           MCBSP_MCR_RMCM_DEFAULT
           ),
#endif
#if(!C64_SUPPORT)
     MCBSP_RCER_RMK(
           MCBSP_RCER_RCEB_DEFAULT,  /* All fields in RCER set to default values */
           MCBSP_RCER_RCEA_DEFAULT
           ),
#endif           
#if(!C64_SUPPORT)
     MCBSP_XCER_RMK(
           MCBSP_XCER_XCEB_DEFAULT,  /* All fields in XCER set to default values */
           MCBSP_XCER_XCEA_DEFAULT
           ),
#endif           

#if (C64_SUPPORT)                 
           MCBSP_RCERE0_RMK(0),      /* Additional registers only for 64x        */
           MCBSP_RCERE1_RMK(0),
           MCBSP_RCERE2_RMK(0),
           MCBSP_RCERE3_RMK(0),
#endif
           
#if (C64_SUPPORT)          
           MCBSP_XCERE0_RMK(0),       /* Additional registers only for 64x       */
           MCBSP_XCERE1_RMK(0),
           MCBSP_XCERE2_RMK(0),
           MCBSP_XCERE3_RMK(0),
#endif
     MCBSP_PCR_RMK(
           MCBSP_PCR_XIOEN_DEFAULT,
           MCBSP_PCR_RIOEN_DEFAULT,
           MCBSP_PCR_FSXM_INTERNAL,  /* Frame sync generated internally     */
           MCBSP_PCR_FSRM_DEFAULT,
           MCBSP_PCR_CLKXM_OUTPUT,   /* tans. clock mode from internal SRGR */
           MCBSP_PCR_CLKRM_DEFAULT,
           MCBSP_PCR_CLKSSTAT_DEFAULT,
           MCBSP_PCR_DXSTAT_DEFAULT,
           MCBSP_PCR_FSXP_DEFAULT,
           MCBSP_PCR_FSRP_DEFAULT,
           MCBSP_PCR_CLKXP_DEFAULT,
           MCBSP_PCR_CLKRP_DEFAULT
           )
}; 

hMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); /* McBSP port 0 */
MCBSP_config(hMcbsp0, &mcbspCfg0);
}

/*--------------------------------------------------------------------------------*/
/* set_interrupts_dma()                                                           */
/*--------------------------------------------------------------------------------*/
#if (DMA_SUPPORT)
void                           /* Set the interrupts */
set_interrupts_dma(void)       /* if the device supports DMA */
{
 IRQ_nmiEnable();
 IRQ_globalEnable();
 IRQ_disable(IRQ_EVT_DMAINT2);  /* INT11 */
 IRQ_clear(IRQ_EVT_DMAINT2);
 IRQ_enable(IRQ_EVT_DMAINT2);
 return;
}
#endif

/*--------------------------------------------------------------------------------*/
/* set_interrupts_edma()                                                          */
/*--------------------------------------------------------------------------------*/

#if (EDMA_SUPPORT)
void                          /* Set the interrupt           */
set_interrupts_edma(void)     /* if the device supports EDMA */
{
 IRQ_nmiEnable();
 IRQ_globalEnable();
 IRQ_reset(IRQ_EVT_EDMAINT);
 IRQ_disable(IRQ_EVT_EDMAINT);
 EDMA_intDisable(12);         /* ch 12 for McBSP transmit event XEVT0 */
 IRQ_clear(IRQ_EVT_EDMAINT);
 EDMA_intClear(12);
 IRQ_enable(IRQ_EVT_EDMAINT);
 EDMA_intEnable(12);

 return;
}
#endif

/*--------------------------------------------------------------------------------*/
/*    DMA DATA TRANSFER COMPLETION ISRs                                           */
/*--------------------------------------------------------------------------------*/
interrupt void     /* vecs.asm hooks this up to IRQ 11 */
c_int11(void)      /* DMA ch2                          */
{
xmit0_done = TRUE;
return;
}

interrupt void    /* vecs.asm hooks this up to IRQ 08 */
c_int08(void)     /* for the EDMA                     */
{
 #if (EDMA_SUPPORT)   
  if (EDMA_intTest(12)) 
  {
  xmit0_done = TRUE;
  EDMA_intClear(12); /* clear CIPR bit so future interrupts can be recognized */
  }
#endif
return;
}
/*-----------------------End of mcbsp_xmit_master.c------------------------------*/