📄 a_law_base.mdl
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Block {
BlockType Logic
Name "Logical\nOperator"
Ports [2, 1]
Position [90, 27, 120, 58]
Operator "XOR"
AllPortsSameDT off
OutDataTypeMode "Boolean"
SampleTime "1/400/2"
}
Block {
BlockType UnitDelay
Name "Unit Delay"
Position [175, 78, 210, 112]
SampleTime "1/400/2"
}
Block {
BlockType Outport
Name "Out1"
Position [300, 43, 330, 57]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Logical\nOperator"
SrcPort 1
Points [25, 0; 0, 5]
Branch {
Points [0, 45]
DstBlock "Unit Delay"
DstPort 1
}
Branch {
DstBlock "Data Type Conversion"
DstPort 1
}
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Logical\nOperator"
DstPort 1
}
Line {
SrcBlock "Unit Delay"
SrcPort 1
Points [15, 0; 0, 50; -155, 0]
DstBlock "Logical\nOperator"
DstPort 2
}
Line {
SrcBlock "Data Type Conversion"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Annotation {
Position [93, 114]
}
}
}
Block {
BlockType SubSystem
Name "Diff_deCode"
Ports [1, 1]
Position [340, 155, 380, 215]
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Diff_deCode"
Location [452, 169, 757, 283]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [25, 23, 55, 37]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Logic
Name "Logical\nOperator2"
Ports [2, 1]
Position [195, 37, 225, 68]
Operator "XOR"
AllPortsSameDT off
OutDataTypeMode "Boolean"
SampleTime "1/400/2"
}
Block {
BlockType UnitDelay
Name "Unit Delay2"
Position [95, 53, 130, 87]
SampleTime "1/400/2"
}
Block {
BlockType Outport
Name "Out1"
Position [250, 48, 280, 62]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Unit Delay2"
SrcPort 1
Points [0, -10]
DstBlock "Logical\nOperator2"
DstPort 2
}
Line {
SrcBlock "In1"
SrcPort 1
Points [0, 0; 15, 0]
Branch {
Points [0, 40]
DstBlock "Unit Delay2"
DstPort 1
}
Branch {
Points [105, 0]
DstBlock "Logical\nOperator2"
DstPort 1
}
}
Line {
SrcBlock "Logical\nOperator2"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "Encode"
Ports [1, 1]
Position [190, 155, 230, 215]
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Encode"
Location [2, 80, 790, 561]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [15, 78, 45, 92]
Orientation "left"
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType SubSystem
Name "Bing_Chuan"
Ports [1, 1]
Position [170, 85, 210, 145]
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Bing_Chuan"
Location [-2, 74, 786, 575]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [125, 223, 155, 237]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType DiscretePulseGenerator
Name "\nGenerator"
Ports [0, 1]
Position [280, 98, 325, 132]
ShowName off
PulseType "Time based"
Period "1/100"
PulseWidth "25"
}
Block {
BlockType Sum
Name "Add"
Ports [4, 1]
Position [480, 113, 485, 332]
Inputs "++++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Demux
Name "Demux"
Ports [1, 4]
Position [190, 118, 195, 337]
BackgroundColor "black"
ShowName off
DisplayOption "bar"
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [350, 122, 380, 153]
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Product1"
Ports [2, 1]
Position [350, 177, 380, 208]
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Product2"
Ports [2, 1]
Position [350, 232, 380, 263]
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Product
Name "Product3"
Ports [2, 1]
Position [350, 287, 380, 318]
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType DiscretePulseGenerator
Name "delay=2/100/4"
Ports [0, 1]
Position [280, 208, 325, 242]
PulseType "Time based"
Period "0.01"
PulseWidth "25"
PhaseDelay "2/100/4"
}
Block {
BlockType DiscretePulseGenerator
Name "delay=3/100/4"
Ports [0, 1]
Position [280, 263, 325, 297]
PulseType "Time based"
Period "0.01"
PulseWidth "25"
PhaseDelay "3/100/4"
}
Block {
BlockType DiscretePulseGenerator
Name "phase delay=1/100/4"
Ports [0, 1]
Position [280, 153, 325, 187]
PulseType "Time based"
Period "0.01"
PulseWidth "25"
PhaseDelay "1/100/4"
}
Block {
BlockType Outport
Name "Out1"
Position [530, 218, 560, 232]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "\nGenerator"
SrcPort 1
Points [0, 15]
DstBlock "Product"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 1
DstBlock "Product"
DstPort 2
}
Line {
SrcBlock "phase delay=1/100/4"
SrcPort 1
Points [0, 15]
DstBlock "Product1"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 2
DstBlock "Product1"
DstPort 2
}
Line {
SrcBlock "delay=2/100/4"
SrcPort 1
Points [0, 15]
DstBlock "Product2"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 3
DstBlock "Product2"
DstPort 2
}
Line {
SrcBlock "delay=3/100/4"
SrcPort 1
Points [0, 15]
DstBlock "Product3"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 4
DstBlock "Product3"
DstPort 2
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Demux"
DstPort 1
}
Line {
SrcBlock "Product"
SrcPort 1
DstBlock "Add"
DstPort 1
}
Line {
SrcBlock "Product1"
SrcPort 1
DstBlock "Add"
DstPort 2
}
Line {
SrcBlock "Product2"
SrcPort 1
DstBlock "Add"
DstPort 3
}
Line {
SrcBlock "Product3"
SrcPort 1
DstBlock "Add"
DstPort 4
}
Line {
SrcBlock "Add"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Annotation {
Name "f=100hz pulsewideh=25 phase delay=0 "
Position [318, 91]
}
Annotation {
Position [565, 207]
}
}
}
Block {
BlockType SubSystem
Name "Pcm"
Ports [1, 1]
Position [110, 85, 150, 145]
NamePlacement "alternate"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Pcm"
Location [2, 80, 790, 581]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [15, 58, 45, 72]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Reference
Name "4Bit\nConverter"
Ports [1, 1]
Position [420, 43, 500, 87]
SourceBlock "commutil2/Integer to Bit\nConverter"
SourceType "Integer to Bit Converter"
nbits "4"
}
Block {
BlockType Reference
Name "A-Law\nCompressor"
Ports [1, 1]
Position [80, 42, 170, 88]
SourceBlock "commsrccod2/A-Law\nCompressor"
SourceType "A-Law Compressor"
ShowPortLabels on
A "87.6"
V "1"
}
Block {
BlockType DataTypeConversion
Name "Data Type Conversion"
Position [305, 48, 380, 82]
OutDataTypeMode "double"
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "Uniform\nEncoder\n4bit"
Ports [1, 1]
Position [200, 44, 270, 86]
SourceBlock "dspquant2/Uniform\nEncoder"
SourceType "Uniform Encoder"
peak "1"
bits "4"
otype "Unsigned integer"
}
Block {
BlockType Outport
Name "Out1"
Position [545, 58, 575, 72]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "A-Law\nCompressor"
SrcPort 1
DstBlock "Uniform\nEncoder\n4bit"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "A-Law\nCompressor"
DstPort 1
}
Line {
SrcBlock "4Bit\nConverter"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "Uniform\nEncoder\n4bit"
SrcPort 1
DstBlock "Data Type Conversion"
DstPort 1
}
Line {
SrcBlock "Data Type Conversion"
SrcPort 1
DstBlock "4Bit\nConverter"
DstPort 1
}
}
}
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