s3c2410.h

UC/OS-II代码

#define UFCON_RX_REQ	(1 << 1)	/* auto-cleared after resetting FIFO */
#define UFCON_FIFO_EN	(1 << 0)	/* FIFO Enable */

#define UMCON_AFC	(1 << 4)	/* Enable Auto Flow Control */
#define UMCON_SEND	(1 << 0)	/* when not-AFC,
						set nRTS 1:'L' 0:'H' level */

#define UTRSTAT_TR_EMP	(1 << 2)	/* 1: Transmitter buffer &
						shifter register empty */
#define UTRSTAT_TX_EMP	(1 << 1)	/* Transmit buffer reg. is empty */
#define UTRSTAT_RX_RDY	(1 << 0)	/* Receive buffer reg. has data */

#define UERSTAT_BRK	(1 << 3)	/* Break receive */
#define UERSTAT_FRAME	(1 << 2)	/* Frame Error */
#define UERSTAT_PARITY	(1 << 1)	/* Parity Error */
#define UERSTAT_OVERRUN	(1 << 0)	/* Overrun Error */

#define UFSTAT_TX_FULL	(1 << 9)	/* Transmit FIFO is full */
#define UFSTAT_RX_FULL	(1 << 8)	/* Receive FIFO is full */

#define fUFSTAT_TX_CNT	Fld(4,4)	/* Number of data in Tx FIFO */
#define UFSTAT_TX_CNT	FMsk(fUFSTAT_TX_CNT)

#define fUFSTAT_RX_CNT	Fld(4,0)	/* Number of data in Rx FIFO */
#define UFSTAT_RX_CNT	FMsk(fUFSTAT_RX_CNT)

#define UMSTAT_dCTS	(1 << 3)	/* see Page 11-16 */
#define UMSTAT_CTS	(1 << 0)	/* CTS(Clear to Send) signal */

#define UTXH_DATA	0x000000FF	/* Transmit data for UARTn */
#define URXH_DATA	0x000000FF	/* Receive data for UARTn */
#define UBRDIVn		0x0000FFFF	/* Baud rate division value (> 0) */
/* UBRDIVn = (int)(PCLK/(bsp * 16)-1 or	UBRDIVn = (int)(UCLK/(bsp * 16)-1 */




#define INT_ADCTC		(1 << 31)	/* ADC EOC interrupt */
#define INT_RTC			(1 << 30)	/* RTC alarm interrupt */
#define INT_SPI1		(1 << 29)	/* UART1 transmit interrupt */
#define INT_UART0		(1 << 28)	/* UART0 transmit interrupt */
#define INT_IIC			(1 << 27)	/* IIC interrupt */
#define INT_USBH		(1 << 26)	/* USB host interrupt */
#define INT_USBD		(1 << 25)	/* USB device interrupt */
#define INT_RESERVED24		(1 << 24)
#define INT_UART1		(1 << 23)	/* UART1 receive interrupt */
#define INT_SPI0		(1 << 22)	/* SPI interrupt */
#define INT_MMC			(1 << 21)	/* MMC interrupt */
#define INT_DMA3		(1 << 20)	/* DMA channel 3 interrupt */
#define INT_DMA2		(1 << 19)	/* DMA channel 2 interrupt */
#define INT_DMA1		(1 << 18)	/* DMA channel 1 interrupt */
#define INT_DMA0		(1 << 17)	/* DMA channel 0 interrupt */
#define INT_LCD			(1 << 16)	/* reserved for future use */
#define INT_UART2		(1 << 15)	/* UART 2 interrupt  */
#define INT_TIMER4		(1 << 14)	/* Timer 4 interrupt */
#define INT_TIMER3		(1 << 13)	/* Timer 3 interrupt */
#define INT_TIMER2		(1 << 12)	/* Timer 2 interrupt */
#define INT_TIMER1		(1 << 11)	/* Timer 1 interrupt */
#define INT_TIMER0		(1 << 10)	/* Timer 0 interrupt */
#define INT_WDT			(1 << 9)	/* Watch-Dog timer interrupt */
#define INT_TICK		(1 << 8)	/* RTC time tick interrupt  */
#define INT_nBAT_FLT		(1 << 7)
#define INT_RESERVED6		(1 << 6)	/* Reserved for future use */
#define INT_EINT8_23		(1 << 5)	/* External interrupt 8 ~ 23 */
#define INT_EINT4_7		(1 << 4)	/* External interrupt 4 ~ 7 */
#define INT_EINT3		(1 << 3)	/* External interrupt 3 */
#define INT_EINT2		(1 << 2)	/* External interrupt 2 */
#define INT_EINT1		(1 << 1)	/* External interrupt 1 */
#define INT_EINT0		(1 << 0)	/* External interrupt 0 */

#define INT_ADC			(1 << 10)
#define INT_TC			(1 << 9)
#define INT_ERR2		(1 << 8)
#define INT_TXD2		(1 << 7)
#define INT_RXD2		(1 << 6)
#define INT_ERR1		(1 << 5)
#define INT_TXD1		(1 << 4)
#define INT_RXD1		(1 << 3)
#define INT_ERR0		(1 << 2)
#define INT_TXD0		(1 << 1)
#define INT_RXD0		(1 << 0)


/* Fields */
#define fRTC_SEC		Fld(7,0)
#define fRTC_MIN		Fld(7,0)
#define fRTC_HOUR		Fld(6,0)
#define fRTC_DAY		Fld(6,0)
#define fRTC_DATE		Fld(2,0)
#define fRTC_MON		Fld(5,0)
#define fRTC_YEAR		Fld(8,0)
/* Mask */
#define Msk_RTCSEC		FMsk(fRTC_SEC)
#define Msk_RTCMIN		FMsk(fRTC_MIN)
#define Msk_RTCHOUR		FMsk(fRTC_HOUR)
#define Msk_RTCDAY		FMsk(fRTC_DAY)
#define Msk_RTCDATE		FMsk(fRTC_DATE)
#define Msk_RTCMON		FMsk(fRTC_MON)
#define Msk_RTCYEAR		FMsk(fRTC_YEAR)
/* bits */
#define RTCCON_EN		(1 << 0) /* RTC Control Enable */
#define RTCCON_CLKSEL		(1 << 1) /* BCD clock as XTAL 1/2^25 clock */
#define RTCCON_CNTSEL		(1 << 2) /* 0: Merge BCD counters */
#define RTCCON_CLKRST		(1 << 3) /* RTC clock count reset */

/* RTC Alarm */
#define RTCALM_GLOBAL		(1 << 6) /* Global alarm enable */
#define RTCALM_YEAR		(1 << 5) /* Year alarm enable */
#define RTCALM_MON		(1 << 4) /* Month alarm enable */
#define RTCALM_DAY		(1 << 3) /* Day alarm enable */
#define RTCALM_HOUR		(1 << 2) /* Hour alarm enable */
#define RTCALM_MIN		(1 << 1) /* Minute alarm enable */
#define RTCALM_SEC		(1 << 0) /* Second alarm enable */
#define RTCALM_EN		(RTCALM_GLOBAL | RTCALM_YEAR | RTCALM_MON |\
				RTCALM_DAY | RTCALM_HOUR | RTCALM_MIN |\
				RTCALM_SEC)
#define RTCALM_DIS		(~RTCALM_EN)


#define fTCFG0_DZONE		Fld(8,16)	/* the dead zone length (= timer 0) */
#define fTCFG0_PRE1		Fld(8,8)	/* prescaler value for time 2,3,4 */
#define fTCFG0_PRE0		Fld(8,0)        /* prescaler value for time 0,1 */
#define fTCON_TIMER0	Fld(5,0)
#define fTCON_TIMER1	Fld(4,8)
#define fTCON_TIMER2	Fld(4,12)
#define fTCON_TIMER3	Fld(4,16)

/* bits */
#define TCFG0_DZONE(x)		FInsrt((x), fTCFG0_DZONE)
#define TCFG0_PRE1(x)		FInsrt((x), fTCFG0_PRE1)
#define TCFG0_PRE0(x)		FInsrt((x), fTCFG0_PRE0)

#define TCON_4_AUTO		(1 << 22)	/* auto reload on/off for Timer 4 */
#define TCON_4_UPDATE		(1 << 21)	/* manual Update TCNTB4 */
#define TCON_4_ONOFF		(1 << 20)	/* 0: Stop, 1: start Timer 4 */
#define COUNT_4_ON		(TCON_4_ONOFF*1)
#define COUNT_4_OFF		(TCON_4_ONOFF*0)
#define TCON_3_AUTO     (1 << 19)       /* auto reload on/off for Timer 3 */
#define TCON_3_INVERT   (1 << 18)       /* 1: Inverter on for TOUT3 */
#define TCON_3_MAN      (1 << 17)       /* manual Update TCNTB3,TCMPB3 */
#define TCON_3_ONOFF    (1 << 16)       /* 0: Stop, 1: start Timer 3 */
#define TCON_2_AUTO     (1 << 15)       /* auto reload on/off for Timer 3 */
#define TCON_2_INVERT   (1 << 14)       /* 1: Inverter on for TOUT3 */
#define TCON_2_MAN      (1 << 13)       /* manual Update TCNTB3,TCMPB3 */
#define TCON_2_ONOFF    (1 << 12)       /* 0: Stop, 1: start Timer 3 */
#define TCON_1_AUTO     (1 << 11)       /* auto reload on/off for Timer 3 */
#define TCON_1_INVERT   (1 << 10)       /* 1: Inverter on for TOUT3 */
#define TCON_1_MAN      (1 << 9)       /* manual Update TCNTB3,TCMPB3 */
#define TCON_1_ONOFF    (1 << 8)       /* 0: Stop, 1: start Timer 3 */
#define TCON_0_AUTO     (1 << 3)       /* auto reload on/off for Timer 3 */
#define TCON_0_INVERT   (1 << 2)       /* 1: Inverter on for TOUT3 */
#define TCON_0_MAN      (1 << 1)       /* manual Update TCNTB3,TCMPB3 */
#define TCON_0_ONOFF    (1 << 0)       /* 0: Stop, 1: start Timer 3 */

#define TIMER3_ATLOAD_ON        (TCON_3_AUTO*1)
#define TIMER3_ATLAOD_OFF       FClrBit(TCON, TCON_3_AUTO)
#define TIMER3_IVT_ON   (TCON_3_INVERT*1)
#define TIMER3_IVT_OFF  (FClrBit(TCON, TCON_3_INVERT))
#define TIMER3_MANUP    (TCON_3_MAN*1)
#define TIMER3_NOP      (FClrBit(TCON, TCON_3_MAN))
#define TIMER3_ON       (TCON_3_ONOFF*1)
#define TIMER3_OFF      (FClrBit(TCON, TCON_3_ONOFF))
#define TIMER2_ATLOAD_ON        (TCON_2_AUTO*1)
#define TIMER2_ATLAOD_OFF       FClrBit(TCON, TCON_2_AUTO)
#define TIMER2_IVT_ON   (TCON_2_INVERT*1)
#define TIMER2_IVT_OFF  (FClrBit(TCON, TCON_2_INVERT))
#define TIMER2_MANUP    (TCON_2_MAN*1)
#define TIMER2_NOP      (FClrBit(TCON, TCON_2_MAN))
#define TIMER2_ON       (TCON_2_ONOFF*1)
#define TIMER2_OFF      (FClrBit(TCON, TCON_2_ONOFF))
#define TIMER1_ATLOAD_ON        (TCON_1_AUTO*1)
#define TIMER1_ATLAOD_OFF       FClrBit(TCON, TCON_1_AUTO)
#define TIMER1_IVT_ON   (TCON_1_INVERT*1)
#define TIMER1_IVT_OFF  (FClrBit(TCON, TCON_1_INVERT))
#define TIMER1_MANUP    (TCON_1_MAN*1)
#define TIMER1_NOP      (FClrBit(TCON, TCON_1_MAN))
#define TIMER1_ON       (TCON_1_ONOFF*1)
#define TIMER1_OFF      (FClrBit(TCON, TCON_1_ONOFF))
#define TIMER0_ATLOAD_ON        (TCON_0_AUTO*1)
#define TIMER0_ATLAOD_OFF       FClrBit(TCON, TCON_0_AUTO)
#define TIMER0_IVT_ON   (TCON_0_INVERT*1)
#define TIMER0_IVT_OFF  (FClrBit(TCON, TCON_0_INVERT))
#define TIMER0_MANUP    (TCON_0_MAN*1)
#define TIMER0_NOP      (FClrBit(TCON, TCON_0_MAN))
#define TIMER0_ON       (TCON_0_ONOFF*1)
#define TIMER0_OFF      (FClrBit(TCON, TCON_0_ONOFF))

#define TCON_TIMER1_CLR   FClrFld(TCON, fTCON_TIMER1);
#define TCON_TIMER2_CLR   FClrFld(TCON, fTCON_TIMER2);
#define TCON_TIMER3_CLR   FClrFld(TCON, fTCON_TIMER3);


/*
 * LCD Controller (Page 15-23)
 *
 * Register
   LCDCON1	LCD Control 1				[word, R/W, 0x00000000]
   LCDCON2	LCD Control 2				[word, R/W, 0x00000000]
   LCDCON3	LCD Control 3				[word, R/W, 0x00000000]
   LCDCON4	LCD Control 4				[word, R/W, 0x00000000]
   LCDCON5	LCD Control 5				[word, R/W, 0x00000000]
   LCDADDR1	STN/TFT: Frame Buffer Start Addr1	[word, R/W, 0x00000000]
   LCDADDR2	STN/TFT: Frame Buffer Start Addr2	[word, R/W, 0x00000000]
   LCDADDR3	STN/TFT: Virtual Screen Address Set	[word, R/W, 0x00000000]
   REDLUT	STN: Red Lookup Table			[word, R/W, 0x00000000]
   GREENLUT	STN: Green Lookup Table			[word, R/W, 0x00000000]
   BLUELUT	STN: Blue Lookup Table			[word, R/W, 0x0000]
   DP1_2	STN: Dithering Pattern Duty 1/2		[word, R/W]
   DP4_7	STN: Dithering Pattern Duty 4/7		[word, R/W]
   DP3_5	STN: Dithering Pattern Duty 3/5		[word, R/W]
   DP2_3	STN: Dithering Pattern Duty 2/3		[word, R/W]
   DP5_7	STN: Dithering Pattern Duty 5/7		[word, R/W]
   DP3_4	STN: Dithering Pattern Duty 3/4		[word, R/W]
   DP4_5	STN: Dithering Pattern Duty 4/5		[word, R/W]
   DP6_7	STN: Dithering Pattern Duty 6/7		[word, R/W]
   DITHMODE	STN: Dithering Mode			[word, R/W, 0x00000000]
   TPAL		TFT: Temporary Pallete			[word, R/W, 0x00000000]
 *
 */


#define fLCD1_LINECNT	Fld(10,18)	/* the status of the line counter */
#define LCD1_LINECNT	FMsk(fLCD_LINECNT)

#define fLCD1_CLKVAL	Fld(10,8)	/* rates of VCLK and CLKVAL[9:0] */
#define LCD1_CLKVAL(x)	FInsrt((x), fLCD1_CLKVAL)
#define LCD1_CLKVAL_MSK	FMask(fLCD1_CLKVAL)

#define LCD1_MMODE (1<<7)

#define fLCD1_PNR	Fld(2,5)	/* select the display mode */
#define LCD1_PNR_4D	FInsrt(0x0, fLCD1_PNR)	/* STN: 4-bit dual scan */
#define LCD1_PNR_4S	FInsrt(0x1, fLCD1_PNR)	/* STN: 4-bit single scan */
#define LCD1_PNR_8S	FInsrt(0x2, fLCD1_PNR)	/* STN: 8-bit single scan */
#define LCD1_PNR_TFT	FInsrt(0x3, fLCD1_PNR)	/* TFT LCD */

#define fLCD1_BPP	Fld(4,1)	/* select BPP(Bit Per Pixel) */
#define LCD1_BPP_1S	FInsrt(0x0, fLCD1_BPP)	/* STN: 1 bpp, mono */
#define LCD1_BPP_2S	FInsrt(0x1, fLCD1_BPP)	/* STN: 2 bpp, 4-grey */
#define LCD1_BPP_4S	FInsrt(0x2, fLCD1_BPP)	/* STN: 4 bpp, 16-grey */
#define LCD1_BPP_8S	FInsrt(0x3, fLCD1_BPP)	/* STN: 8 bpp, color */
#define LCD1_BPP_12S	FInsrt(0x4, fLCD1_BPP)	/* STN: 12 bpp, color */
#define LCD1_BPP_1T	FInsrt(0x8, fLCD1_BPP)	/* TFT: 1 bpp */
#define LCD1_BPP_2T	FInsrt(0x9, fLCD1_BPP)	/* TFT: 2 bpp */
#define LCD1_BPP_4T	FInsrt(0xa, fLCD1_BPP)	/* TFT: 4 bpp */
#define LCD1_BPP_8T	FInsrt(0xb, fLCD1_BPP)	/* TFT: 8 bpp */
#define LCD1_BPP_16T	FInsrt(0xc, fLCD1_BPP)	/* TFT: 16 bpp */

#define LCD1_ENVID	(1 << 0)	/* 1: Enable the video output */

#define fLCD2_VBPD	Fld(8,24)	/* TFT: (Vertical Back Porch)
	   # of inactive lines at the start of a frame,
	   after vertical synchronization period. */
//#define LCD2_VBPD	FMsk(fLCD2_VBPD)
#define LCD2_VBPD(x)	FInsrt((x), fLCD2_VBPD)

#define fLCD2_LINEVAL	Fld(10,14)	/* TFT/STN: vertical size of LCD */
#define LCD2_LINEVAL(x)	FInsrt((x), fLCD2_LINEVAL)
#define LCD2_LINEVAL_MSK	FMsk(fLCD2_LINEVAL)

#define fLCD2_VFPD	Fld(8,6)	/* TFT: (Vertical Front Porch)
	   # of inactive lines at the end of a frame,
	   before vertical synchronization period. */
//#define LCD2_VFPD	FMsk(fLCD2_VFPD)
#define LCD2_VFPD(x)	FInsrt((x), fLCD2_VFPD)

#define fLCD2_VSPW	Fld(6,0)	/* TFT: (Vertical Sync Pulse Width)
	   the VSYNC pulse's high level width
	   by counting the # of inactive lines */
//#define LCD2_VSPW	FMsk(fLCD2_VSPW)
#define LCD2_VSPW(x)	FInsrt((x), fLCD2_VSPW)

#define fLCD3_HBPD	Fld(7,19)	/* TFT: (Horizontal Back Porch)
	   # of VCLK periods between the falling edge of HSYNC
	   and the start of active data */
//#define LCD3_HBPD	FMsk(fLCD3_HBPD)
#define LCD3_HBPD(x)	FInsrt((x), fLCD3_HBPD)

#define fLCD3_WDLY	Fld(7,19)	/* STN: delay between VLINE and
	   VCLK by counting the # of the HCLK */
#define LCD3_WDLY	FMsk(fLCD3_WDLY)
#define LCD3_WDLY	FMsk(fLCD3_WDLY)
#define LCD3_WDLY_16	FInsrt(0x0, fLCD3_WDLY)	/* 16 clock */
#define LCD3_WDLY_32	FInsrt(0x1, fLCD3_WDLY)	/* 32 clock */
#define LCD3_WDLY_64	FInsrt(0x2, fLCD3_WDLY)	/* 64 clock */
#define LCD3_WDLY_128	FInsrt(0x3, fLCD3_WDLY)	/* 128 clock */

#define fLCD3_HOZVAL	Fld(11,8)	/* horizontal size of LCD */
//#define LCD3_HOZVAL	FMsk(fLCD3_HOZVAL)
#define LCD3_HOZVAL(x)	FInsrt((x), fLCD3_HOZVAL)
#define LCD3_HOZVAL_MSK	FMsk(fLCD3_HOZVAL)

#define fLCD3_HFPD	Fld(8,0)	/* TFT: (Horizontal Front Porch)
	   # of VCLK periods between the end of active date
	   and the rising edge of HSYNC */
//#define LCD3_HFPD	FMsk(LCD3_HFPD)
#define LCD3_HFPD(x)	FInsrt((x), fLCD3_HFPD)

#define fLCD3_LINEBLNK	Fld(8,0)	/* STN: the blank time
	   in one horizontal line duration time.
	   the unit of LINEBLNK is HCLK x 8 */
//#define LCD3_LINEBLNK	FMsk(fLCD3_LINEBLNK)
#define LCD3_LINEBLNK	FInsrt(fLCD3_LINEBLNK)

#if 0
#define LCD4_PALADDEN	(1 << 24)	/* TFT: enable Pallete index offset */

#define fLCD4_ADDVAL	Fld(8,16)	/* TFT: Pallete index offset */
#define LCD4_ADDVAL	FMsk(fLCD4_ADDVAL)
#endif

#define fLCD4_MVAL	Fld(8,8)	/* STN: the rate at which the VM signal