nandfmd.h
来自「nand flash 测试程序」· C头文件 代码 · 共 227 行
H
227 行
//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2004-2007, Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
// File: nandfmd.h
//
// Contains definitions for FMD impletation of the SoC NAND flash controller
// and NAND memory device.
//
//------------------------------------------------------------------------------
#ifndef __NANDFMD_H__
#define __NANDFMD_H__
//#define K9F1G08U0B
#ifdef K9F1G08U0B
//--------------------------------------------------------------------
// File: K9F1G08U0B.h
#define NAND_BLOCK_CNT (1024) // 1024 blocks
#define NAND_SECTOR_CNT (64) // Each Block has 64 Pages
#define NAND_SECTOR_SIZE (2048) // Each Page has 1088 Bytes
#define NAND_SECTORS_PERPAGE (1) // Each Page has 1 Sectors
#define NAND_SPARE_SIZE (16)
#define NAND_BLOCK_SIZE (NAND_SECTOR_CNT * NAND_SECTOR_SIZE)
#define NAND_BBI_OFFSET 5 // Bad block info spare offset
#define NAND_BUS_WIDTH 8 // 8-bit bus
#define NAND_MAKER_CODE 0xEC // Samsung
#define NAND_DEVICE_CODE 0x71
#define NAND_STATUS_MASK_ERROR (1U << 0) // Status Bit0 indicates error
#define NAND_ID_CODE ((NAND_DEVICE_CODE << 8) | NAND_MAKER_CODE)
// K9F1G08U0B address is sent in 4-cycles
// 1st Cycle: Column address A[7:0]
// 2nd Cycle: Column address A[8:11]
// 3rd Cycle: Page address A[12:19]
// 4th Cycle: Page address A[20:27]
#define NF_ADDR_COL(addr) { NF_ADDR((addr) & 0xFF); \
NF_ADDR(((addr) >> 8) & 0x0F) }
#define NF_ADDR_PAGE(addr) { NF_ADDR(((addr) >> 12) & 0xFF);\
NF_ADDR(((addr) >> 20) & 0xFF); }
// K9F1G08U0B supports sequential row and serial page access, so we only
// need to send read command and address on first access.
#define NF_READ_SEQ(sectAddr) (TRUE)
#else
//--------------------------------------------------------------------
//--------------- File: K9F1208XXX.h---------------------------------
#define NAND_BLOCK_CNT (4096) // 4096 blocks
#define NAND_SECTOR_CNT (32) // Each Block has 32 Pages
#define NAND_SECTOR_SIZE (512) // Each Page has 512 Bytes
#define NAND_SECTORS_PERPAGE (1) // Each Page has 1 Sectors
#define NAND_SPARE_SIZE (16)
#define NAND_BLOCK_SIZE (NAND_SECTOR_CNT * NAND_SECTOR_SIZE)
#define NAND_BBI_OFFSET 5 // Bad block info spare offset
#define NAND_BUS_WIDTH 8 // 8-bit bus
#define NAND_MAKER_CODE 0xEC // Samsung
#define NAND_DEVICE_CODE 0x76 //K9F1208U0B
#define NAND_STATUS_MASK_ERROR (1U << 0) // Status Bit0 indicates error
#define NAND_ID_CODE ((NAND_DEVICE_CODE << 8) | NAND_MAKER_CODE)
// K9F1208X0C address is sent in 4-cycles
// 1st Cycle: Column address A[7:0]
// 2nd Cycle: Page address A[16:9]
// 3rd Cycle: Page address A[24:17]
// 4th Cycle: Page address A[26:25]
#define NF_ADDR_COL(addr) { NF_ADDR((addr) & 0xFF); }
#define NF_ADDR_PAGE(addr) { NF_ADDR((addr) & 0xFF); \
NF_ADDR(((addr) >> 8) & 0xFF); \
NF_ADDR(((addr) >> 16) & 0x3); }
// TODO:
// K9F1208X0C supports sequential row and serial page access, so we only
// need to send read command and address on first access.
#define NF_READ_SEQ(sectAddr) (TRUE)
#endif
//--------------------------------------------------------------------
#define CMD_READID 0x90 // Read ID
#define CMD_READ 0x00 // Read data field
#define CMD_READ_2CYCLE 0x30 // Read data 2nd cycle
#define CMD_READ2 0x50 // Read spare field
#define CMD_RESET 0xFF // Reset
#define CMD_ERASE 0x60 // Erase setup
#define CMD_ERASE2 0xD0 // Erase
#define CMD_WRITE 0x80 // Sequential data input
#define CMD_WRITE2 0x10 // Program
#define CMD_STATUS 0x70 // Read status
#define OUTREG16(reg,val) (*((volatile u16 *)(reg)) = (val))
#define OUTREG32(reg,val) (*((volatile u32 *)(reg)) = (val))
#define INREG16(reg) (*(volatile u16 *)(reg))
#define INREG32(reg) (*(volatile u32 *)(reg))
#define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y))
#define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y))
#define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y))
#define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y))
#define CSP_BITFMASK(bit) (1U << (bit))
#define CSP_BITFVAL(bit, val) ((val) << (bit))
#define NF_CMD(cmd) { OUTREG16(&g_pNFC->NAND_FLASH_CMD, (cmd)); \
OUTREG16(&g_pNFC->NAND_FLASH_CONFIG2, CSP_BITFMASK(NANDFC_NAND_FLASH_CONFIG2_FCMD)); \
NFCWait(TRUE); }
#define NF_ADDR(addr) { OUTREG16(&g_pNFC->NAND_FLASH_ADD, (addr)); \
OUTREG16(&g_pNFC->NAND_FLASH_CONFIG2, CSP_BITFMASK(NANDFC_NAND_FLASH_CONFIG2_FADD)); \
NFCWait(TRUE); }
#define NF_RD_PAGE() { CLRREG16(&g_pNFC->NAND_FLASH_CONFIG1, CSP_BITFMASK(NANDFC_NAND_FLASH_CONFIG1_SP_EN)); \
OUTREG16(&g_pNFC->NAND_FLASH_CONFIG2, CSP_BITFMASK(NANDFC_NAND_FLASH_CONFIG2_FDO_PAGE)); \
NFCWait(TRUE); }
#define NF_RD_SPARE() { SETREG16(&g_pNFC->NAND_FLASH_CONFIG1, CSP_BITFMASK(NANDFC_NAND_FLASH_CONFIG1_SP_EN)); \
OUTREG16(&g_pNFC->NAND_FLASH_CONFIG2, CSP_BITFMASK(NANDFC_NAND_FLASH_CONFIG2_FDO_PAGE)); \
NFCWait(TRUE); }
#define NF_WR_PAGE() { CLRREG16(&g_pNFC->NAND_FLASH_CONFIG1, CSP_BITFMASK(NANDFC_NAND_FLASH_CONFIG1_SP_EN)); \
OUTREG16(&g_pNFC->NAND_FLASH_CONFIG2, CSP_BITFMASK(NANDFC_NAND_FLASH_CONFIG2_FDI)); \
NFCWait(TRUE); }
#define NF_WR_SPARE() { SETREG16(&g_pNFC->NAND_FLASH_CONFIG1, CSP_BITFMASK(NANDFC_NAND_FLASH_CONFIG1_SP_EN)); \
OUTREG16(&g_pNFC->NAND_FLASH_CONFIG2, CSP_BITFMASK(NANDFC_NAND_FLASH_CONFIG2_FDI)); \
NFCWait(TRUE); }
#define NF_RD_ID() { CLRREG16(&g_pNFC->NAND_FLASH_CONFIG1, CSP_BITFMASK(NANDFC_NAND_FLASH_CONFIG1_SP_EN)); \
OUTREG16(&g_pNFC->NAND_FLASH_CONFIG2, CSP_BITFMASK(NANDFC_NAND_FLASH_CONFIG2_FDO_ID)); \
NFCWait(TRUE); }
#define NF_RD_STATUS() { CLRREG16(&g_pNFC->NAND_FLASH_CONFIG1, CSP_BITFMASK(NANDFC_NAND_FLASH_CONFIG1_SP_EN)); \
OUTREG16(&g_pNFC->NAND_FLASH_CONFIG2, CSP_BITFMASK(NANDFC_NAND_FLASH_CONFIG2_FDO_STATUS)); \
NFCWait(TRUE); }
#define NFC_BASE_ADDR 0xD8000000
/*
* Addresses for NFC registers
*/
#define NFC_BUF_SIZE (*((volatile u16 *)(NFC_BASE_ADDR + 0xE00)))
#define NFC_BUF_ADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE04)))
#define NFC_FLASH_ADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE06)))
#define NFC_FLASH_CMD (*((volatile u16 *)(NFC_BASE_ADDR + 0xE08)))
#define NFC_CONFIG (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0A)))
#define NFC_ECC_STATUS_RESULT (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0C)))
#define NFC_RSLTMAIN_AREA (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0E)))
#define NFC_RSLTSPARE_AREA (*((volatile u16 *)(NFC_BASE_ADDR + 0xE10)))
#define NFC_WRPROT (*((volatile u16 *)(NFC_BASE_ADDR + 0xE12)))
#define NFC_UNLOCKSTART_BLKADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE14)))
#define NFC_UNLOCKEND_BLKADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE16)))
#define NFC_NF_WRPRST (*((volatile u16 *)(NFC_BASE_ADDR + 0xE18)))
#define NFC_CONFIG1 (*((volatile u16 *)(NFC_BASE_ADDR + 0xE1A)))
#define NFC_CONFIG2 (*((volatile u16 *)(NFC_BASE_ADDR + 0xE1C)))
/*!
* Addresses for NFC RAM BUFFER Main area 0
*/
#define MAIN_AREA0 (volatile u16 *)(NFC_BASE_ADDR + 0x000)
#define MAIN_AREA1 (volatile u16 *)(NFC_BASE_ADDR + 0x200)
/*!
* Addresses for NFC SPARE BUFFER Spare area 0
*/
#define SPARE_AREA0 (volatile u16 *)(NFC_BASE_ADDR + 0x800)
// Include NAND memory device definitions
#ifdef BSP_NAND_K9K1G08U0B
#include "K9K1G08U0B.h"
#endif
#ifdef BSP_NAND_K9F1G08U0A
#include "K9F1G08U0A.h"
#endif
#ifdef BSP_NAND_K9K2G08U0A
#include "K9K2G08U0A.h"
#endif
#ifdef BSP_NAND_K9F1208X0C
#include "K9F1208X0C.h"
#endif
PCSP_NANDFC_REGS g_pNFC;
typedef struct _SectorInfo
{
u32 dwReserved1; // Reserved - used by FAL
u8 bOEMReserved; // For use by OEM
u8 bBadBlock; // Indicates if block is BAD
u16 wReserved2; // Reserved - used by FAL
}SectorInfo, *PSectorInfo;
// FMD block status definitions.
#define BLOCK_STATUS_UNKNOWN 0x01
#define BLOCK_STATUS_BAD 0x02
#define BLOCK_STATUS_READONLY 0x04
#define BLOCK_STATUS_RESERVED 0x08
// FMD OEM reserved area bitfield.
#define OEM_BLOCK_RESERVED 0x01
#define OEM_BLOCK_READONLY 0x02
#endif // __NANDFMD_H__
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?