📄 armvic.lst
字号:
1 .file "armVIC.c"
9 .Ltext0:
10 .align 2
11 .global enableFIQ
13 enableFIQ:
14 .LFB9:
15 .file 1 "armVIC.c"
1:armVIC.c **** /******************************************************************************
2:armVIC.c **** *
3:armVIC.c **** * $RCSfile: $
4:armVIC.c **** * $Revision: $
5:armVIC.c **** *
6:armVIC.c **** * This module provides the interface routines for setting up and
7:armVIC.c **** * controlling the various interrupt modes present on the ARM processor.
8:armVIC.c **** * Copyright 2004, R O SoftWare
9:armVIC.c **** * No guarantees, warrantees, or promises, implied or otherwise.
10:armVIC.c **** * May be used for hobby or commercial purposes provided copyright
11:armVIC.c **** * notice remains intact.
12:armVIC.c **** *
13:armVIC.c **** *****************************************************************************/
14:armVIC.c **** #include "types.h"
15:armVIC.c **** #include "armVIC.h"
16:armVIC.c ****
17:armVIC.c **** #define IRQ_MASK 0x00000080
18:armVIC.c **** #define FIQ_MASK 0x00000040
19:armVIC.c **** #define INT_MASK (IRQ_MASK | FIQ_MASK)
20:armVIC.c ****
21:armVIC.c **** static inline unsigned __get_cpsr(void)
22:armVIC.c **** {
23:armVIC.c **** unsigned long retval;
24:armVIC.c **** asm volatile (" mrs %0, cpsr" : "=r" (retval) : /* no inputs */ );
25:armVIC.c **** return retval;
26:armVIC.c **** }
27:armVIC.c ****
28:armVIC.c **** static inline void __set_cpsr(unsigned val)
29:armVIC.c **** {
30:armVIC.c **** asm volatile (" msr cpsr, %0" : /* no outputs */ : "r" (val) );
31:armVIC.c **** }
32:armVIC.c ****
33:armVIC.c **** unsigned disableIRQ(void)
34:armVIC.c **** {
35:armVIC.c **** unsigned _cpsr;
36:armVIC.c ****
37:armVIC.c **** _cpsr = __get_cpsr();
38:armVIC.c **** __set_cpsr(_cpsr | IRQ_MASK);
39:armVIC.c **** return _cpsr;
40:armVIC.c **** }
41:armVIC.c ****
42:armVIC.c **** unsigned restoreIRQ(unsigned oldCPSR)
43:armVIC.c **** {
44:armVIC.c **** unsigned _cpsr;
45:armVIC.c ****
46:armVIC.c **** _cpsr = __get_cpsr();
47:armVIC.c **** __set_cpsr((_cpsr & ~IRQ_MASK) | (oldCPSR & IRQ_MASK));
48:armVIC.c **** return _cpsr;
49:armVIC.c **** }
50:armVIC.c ****
51:armVIC.c **** unsigned enableIRQ(void)
52:armVIC.c **** {
53:armVIC.c **** unsigned _cpsr;
54:armVIC.c ****
55:armVIC.c **** _cpsr = __get_cpsr();
56:armVIC.c **** __set_cpsr(_cpsr & ~IRQ_MASK);
57:armVIC.c **** return _cpsr;
58:armVIC.c **** }
59:armVIC.c ****
60:armVIC.c **** unsigned disableFIQ(void)
61:armVIC.c **** {
62:armVIC.c **** unsigned _cpsr;
63:armVIC.c ****
64:armVIC.c **** _cpsr = __get_cpsr();
65:armVIC.c **** __set_cpsr(_cpsr | FIQ_MASK);
66:armVIC.c **** return _cpsr;
67:armVIC.c **** }
68:armVIC.c ****
69:armVIC.c **** unsigned restoreFIQ(unsigned oldCPSR)
70:armVIC.c **** {
71:armVIC.c **** unsigned _cpsr;
72:armVIC.c ****
73:armVIC.c **** _cpsr = __get_cpsr();
74:armVIC.c **** __set_cpsr((_cpsr & ~FIQ_MASK) | (oldCPSR & FIQ_MASK));
75:armVIC.c **** return _cpsr;
76:armVIC.c **** }
77:armVIC.c ****
78:armVIC.c **** unsigned enableFIQ(void)
79:armVIC.c **** {
16 args = 0, pretend = 0, frame = 0
17 @ frame_needed = 0, uses_anonymous_args = 0
18 @ link register save eliminated.
19 .LVL0:
20 @ lr needed for prologue
21 .LBB2:
22 .LBB3:
23 .loc 1 24 0
24 mrs r0, cpsr
25 0000 00000FE1 .LVL1:
26 .LBE3:
27 .LBE2:
28 .LBB4:
29 .loc 1 30 0
30 bic r3, r0, #64
31 0004 4030C0E3 msr cpsr, r3
32 0008 03F029E1 .LVL2:
33 .LBE4:
34 .loc 1 85 0
80:armVIC.c **** unsigned _cpsr;
81:armVIC.c ****
82:armVIC.c **** _cpsr = __get_cpsr();
83:armVIC.c **** __set_cpsr(_cpsr & ~FIQ_MASK);
84:armVIC.c **** return _cpsr;
85:armVIC.c **** }
35 e enableFIQ, .-enableFIQ
36 000c 1EFF2FE1 .align 2
37 .global disableIRQ
39 disableIRQ:
40 .LFB4:
41 .loc 1 34 0
42 @ args = 0, pretend = 0, frame = 0
43 @ frame_needed = 0, uses_anonymous_args = 0
44 @ link register save eliminated.
45 .LVL3:
46 @ lr needed for prologue
47 .LBB5:
48 .LBB6:
49 .loc 1 24 0
50 mrs r0, cpsr
51 .LVL4:
52 .LBE6:
53 0010 00000FE1 .LBE5:
54 .LBB7:
55 .loc 1 30 0
56 orr r3, r0, #128
57 msr cpsr, r3
58 .LVL5:
59 0014 803080E3 .LBE7:
60 0018 03F029E1 .loc 1 40 0
61 bx lr
62 .LFE4:
64 001c 1EFF2FE1 .align 2
65 .global restoreIRQ
67 restoreIRQ:
68 .LFB5:
69 .loc 1 43 0
70 @ args = 0, pretend = 0, frame = 0
71 @ frame_needed = 0, uses_anonymous_args = 0
72 @ link register save eliminated.
73 .LVL6:
74 @ lr needed for prologue
75 .LBB8:
76 .LBB9:
77 .loc 1 24 0
78 mrs r2, cpsr
79 .LVL7:
80 .LBE9:
81 0020 00200FE1 .LBE8:
82 .LBB10:
83 .loc 1 30 0
84 and r0, r0, #128
85 .LVL8:
86 bic r3, r2, #128
87 0024 800000E2 orr r3, r3, r0
88 msr cpsr, r3
89 0028 8030C2E3 .LBE10:
90 002c 003083E1 .loc 1 49 0
91 0030 03F029E1 mov r0, r2
92 bx lr
93 .LFE5:
95 0038 1EFF2FE1 .align 2
96 .global enableIRQ
98 enableIRQ:
99 .LFB6:
100 .loc 1 52 0
101 @ args = 0, pretend = 0, frame = 0
102 @ frame_needed = 0, uses_anonymous_args = 0
103 @ link register save eliminated.
104 .LVL9:
105 @ lr needed for prologue
106 .LBB11:
107 .LBB12:
108 .loc 1 24 0
109 mrs r0, cpsr
110 .LVL10:
111 .LBE12:
112 003c 00000FE1 .LBE11:
113 .LBB13:
114 .loc 1 30 0
115 bic r3, r0, #128
116 msr cpsr, r3
117 .LVL11:
118 0040 8030C0E3 .LBE13:
119 0044 03F029E1 .loc 1 58 0
120 bx lr
121 .LFE6:
123 0048 1EFF2FE1 .align 2
124 .global disableFIQ
126 disableFIQ:
127 .LFB7:
128 .loc 1 61 0
129 @ args = 0, pretend = 0, frame = 0
130 @ frame_needed = 0, uses_anonymous_args = 0
131 @ link register save eliminated.
132 .LVL12:
133 @ lr needed for prologue
134 .LBB14:
135 .LBB15:
136 .loc 1 24 0
137 mrs r0, cpsr
138 .LVL13:
139 .LBE15:
140 004c 00000FE1 .LBE14:
141 .LBB16:
142 .loc 1 30 0
143 orr r3, r0, #64
144 msr cpsr, r3
145 .LVL14:
146 0050 403080E3 .LBE16:
147 0054 03F029E1 .loc 1 67 0
148 bx lr
149 .LFE7:
151 0058 1EFF2FE1 .align 2
152 .global restoreFIQ
154 restoreFIQ:
155 .LFB8:
156 .loc 1 70 0
157 @ args = 0, pretend = 0, frame = 0
158 @ frame_needed = 0, uses_anonymous_args = 0
159 @ link register save eliminated.
160 .LVL15:
161 @ lr needed for prologue
162 .LBB17:
163 .LBB18:
164 .loc 1 24 0
165 mrs r2, cpsr
166 .LVL16:
167 .LBE18:
168 005c 00200FE1 .LBE17:
169 .LBB19:
170 .loc 1 30 0
171 and r0, r0, #64
172 .LVL17:
173 bic r3, r2, #64
174 0060 400000E2 orr r3, r3, r0
175 msr cpsr, r3
176 0064 4030C2E3 .LBE19:
177 0068 003083E1 .loc 1 76 0
178 006c 03F029E1 mov r0, r2
179 bx lr
180 .LFE8:
182 0074 1EFF2FE1 .section .debug_frame,"",%progbits
183 .Lframe0:
184 .4byte .LECIE0-.LSCIE0
249 .LLST0:
DEFINED SYMBOLS
*ABS*:00000000 armVIC.c
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/ccgnaaaa.s:13 .text:00000000 enableFIQ
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/ccgnaaaa.s:25 .text:00000000 $a
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/ccgnaaaa.s:42 .text:00000010 disableIRQ
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/ccgnaaaa.s:70 .text:00000020 restoreIRQ
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/ccgnaaaa.s:101 .text:0000003c enableIRQ
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/ccgnaaaa.s:129 .text:0000004c disableFIQ
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/ccgnaaaa.s:157 .text:0000005c restoreFIQ
NO UNDEFINED SYMBOLS
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