📄 uartisr.lst
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125:uartISR.c **** #endif // UART1_RX_INT_MODE
126:uartISR.c ****
127:uartISR.c **** #ifdef UART1_TX_INT_MODE
128:uartISR.c **** extern uint8_t uart1_tx_buffer[UART1_TX_BUFFER_SIZE];
129:uartISR.c **** extern uint16_t uart1_tx_insert_idx, uart1_tx_extract_idx;
130:uartISR.c **** extern int uart1_tx_running;
131:uartISR.c **** #endif // UART1_TX_INT_MODE
132:uartISR.c ****
133:uartISR.c **** #if defined(UART1_TX_INT_MODE) || defined(UART1_RX_INT_MODE)
134:uartISR.c **** /******************************************************************************
135:uartISR.c **** *
136:uartISR.c **** * Function Name: uart1ISR()
137:uartISR.c **** *
138:uartISR.c **** * Description:
139:uartISR.c **** * This function implements the ISR for UART1.
140:uartISR.c **** *
141:uartISR.c **** * Calling Sequence:
142:uartISR.c **** * void
143:uartISR.c **** *
144:uartISR.c **** * Returns:
145:uartISR.c **** * void
146:uartISR.c **** *
147:uartISR.c **** *****************************************************************************/
148:uartISR.c **** void uart1ISR(void)
149:uartISR.c **** {
179 lr, lr,#4
180 stmfd sp!,{r0-r12,lr}
181 mrs r1, spsr
182 stmfd sp!,{r1}
183 .LBB5:
150:uartISR.c **** uint8_t iid;
151:uartISR.c ****
152:uartISR.c **** // perform proper ISR entry so thumb-interwork works properly
153:uartISR.c **** ISR_ENTRY();
184 1 177 0
185 0184 04E04EE2 ldr r3, .L57
186 0188 FF5F2DE9 ldrh r6, [r3, #0]
187 018c 00104FE1 .LBE5:
188 0190 02002DE9 .loc 1 190 0
189 ldr r3, .L57+4
154:uartISR.c ****
155:uartISR.c **** // loop until not more interrupt sources
156:uartISR.c **** while (((iid = U1IIR) & UIIR_NO_INT) == 0)
157:uartISR.c **** {
158:uartISR.c **** // identify & process the highest priority interrupt
159:uartISR.c **** switch (iid & UIIR_ID_MASK)
160:uartISR.c **** {
161:uartISR.c **** case UIIR_RLS_INT: // Receive Line Status
162:uartISR.c **** U1LSR; // read LSR to clear
163:uartISR.c **** break;
164:uartISR.c ****
165:uartISR.c **** #ifdef UART1_RX_INT_MODE
166:uartISR.c **** case UIIR_CTI_INT: // Character Timeout Indicator
167:uartISR.c **** case UIIR_RDA_INT: // Receive Data Available
168:uartISR.c **** do
169:uartISR.c **** {
170:uartISR.c **** uint16_t temp;
171:uartISR.c ****
172:uartISR.c **** // calc next insert index & store character
173:uartISR.c **** temp = (uart1_rx_insert_idx + 1) % UART1_RX_BUFFER_SIZE;
174:uartISR.c **** uart1_rx_buffer[uart1_rx_insert_idx] = U1RBR;
175:uartISR.c ****
176:uartISR.c **** // check for more room in queue
177:uartISR.c **** if (temp != uart1_rx_extract_idx)
190 r5, [r3, #0]
191 0194 54319FE5 ldr r3, .L57+8
192 0198 B060D3E1 ldr r4, [r3, #0]
193 ldr r3, .L57+12
178:uartISR.c **** uart1_rx_insert_idx = temp; // update insert index
179:uartISR.c **** }
180:uartISR.c **** while (U1LSR & ULSR_RDR);
181:uartISR.c ****
182:uartISR.c **** break;
183:uartISR.c **** #endif
184:uartISR.c ****
185:uartISR.c **** #ifdef UART1_TX_INT_MODE
186:uartISR.c **** case UIIR_THRE_INT: // Transmit Holding Register Empty
187:uartISR.c **** while (U1LSR & ULSR_THRE)
188:uartISR.c **** {
189:uartISR.c **** // check if more data to send
190:uartISR.c **** if (uart1_tx_insert_idx != uart1_tx_extract_idx)
194 h r0, [r3, #0]
195 019c 50319FE5 ldr r3, .L57+16
196 01a0 B050D3E1 ldrh ip, [r3, #0]
197 01a4 4C319FE5 .LVL9:
198 01a8 004093E5 b .L56
199 01ac 48319FE5 .L31:
200 01b0 B000D3E1 .loc 1 159 0
201 01b4 44319FE5 and r3, r2, #14
202 01b8 B0C0D3E1 cmp r3, #12
203 ldrls pc, [pc, r3, asl #2]
204 01bc 3B0000EA b .L32
205 .p2align 2
206 .L37:
207 01c0 0E3002E2 .word .L33
208 01c4 0C0053E3 .word .L32
209 01c8 03F19F97 .word .L53
210 01cc 330000EA .word .L32
211 .word .L50
212 .word .L32
213 01d0 90020000 .word .L36
214 01d4 A0020000 .word .L32
215 01d8 78020000 .word .L32
216 01dc A0020000 .word .L32
217 01e0 10020000 .word .L32
218 01e4 A0020000 .word .L32
219 01e8 04020000 .word .L50
220 01ec A0020000 .L36:
221 01f0 A0020000 .loc 1 162 0
222 01f4 A0020000 ldr r3, .L57+20
223 01f8 A0020000 ldrb r3, [r3, #20] @ zero_extendqisi2
224 01fc A0020000 b .L56
225 0200 10020000 .LVL10:
226 .L50:
227 .LBB6:
228 0204 F8309FE5 .loc 1 173 0
229 0208 1430D3E5 ldr r1, .L57+24
230 020c 270000EA add r3, ip, #1
231 .LVL11:
232 and r1, r3, r1
233 cmp r1, #0
234 .loc 1 174 0
235 0210 F0109FE5 ldr lr, .L57+20
236 0214 01308CE2 .loc 1 173 0
237 sublt r1, r1, #1
238 0218 011003E0 mvnlt r1, r1, asl #25
239 021c 000051E3 .loc 1 174 0
240 ldrb r2, [lr, #0] @ zero_extendqisi2
241 0220 DCE09FE5 ldr r3, .L57+28
242 .loc 1 173 0
243 0224 011041B2 mvnlt r1, r1, lsr #25
244 0228 811CE0B1 .loc 1 174 0
245 strb r2, [ip, r3]
246 022c 0020DEE5 .loc 1 173 0
247 0230 D4309FE5 addlt r1, r1, #1
248 mov r3, r1, asl #16
249 0234 A11CE0B1 mov r3, r3, lsr #16
250 .LVL12:
251 0238 0320CCE7 .LBE6:
252 .loc 1 180 0
253 023c 011081B2 ldrb r2, [lr, #20] @ zero_extendqisi2
254 0240 0138A0E1 .LBB7:
255 0244 2338A0E1 .loc 1 177 0
256 cmp r3, r6
257 movne ip, r3
258 .LBE7:
259 0248 1420DEE5 .loc 1 180 0
260 tst r2, #1
261 beq .L56
262 024c 060053E1 b .L50
263 0250 03C0A011 .LVL13:
264 .L41:
265 .loc 1 190 0
266 0254 010012E3 cmp r5, r0
267 0258 1400000A beq .L47
268 025c EBFFFFEA .loc 1 192 0
269 ldr r3, .L57+32
270 ldrb r3, [r0, r3] @ zero_extendqisi2
271 strb r3, [r1, #0]
272 0260 000055E1 .loc 1 193 0
273 0264 0B00000A and r0, r2, #127
191:uartISR.c **** {
192:uartISR.c **** U1THR = uart1_tx_buffer[uart1_tx_extract_idx++];
274 r3, #32
275 0268 A0309FE5 .loc 1 193 0
276 026c 0330D0E7 add r2, r0, #1
277 0270 0030C1E5 .loc 1 187 0
193:uartISR.c **** uart1_tx_extract_idx %= UART1_TX_BUFFER_SIZE;
278 .L41
279 0274 7F0002E2 b .L56
280 .L33:
281 .loc 1 207 0
282 0278 84109FE5 ldr r3, .L57+20
283 027c 1430D1E5 b .L55
284 0280 200013E3 .L47:
285 .loc 1 190 0
286 0284 012080E2 mov r4, #0
287 b .L56
288 0288 F4FFFF1A .L32:
289 028c 070000EA .loc 1 211 0
290 ldr r3, .L57+20
194:uartISR.c **** }
195:uartISR.c **** else
196:uartISR.c **** {
197:uartISR.c **** // no
198:uartISR.c **** uart1_tx_running = 0; // clear running flag
199:uartISR.c **** break;
200:uartISR.c **** }
201:uartISR.c **** }
202:uartISR.c ****
203:uartISR.c **** break;
204:uartISR.c **** #endif // UART1_TX_INT_MODE
205:uartISR.c ****
206:uartISR.c **** case UIIR_MS_INT: // MODEM Status
207:uartISR.c **** U1MSR; // read MSR to clear
291 , #20] @ zero_extendqisi2
292 0290 6C309FE5 .loc 1 212 0
293 0294 040000EA ldrb r2, [r3, #0] @ zero_extendqisi2
294 .L55:
295 .loc 1 213 0
296 0298 0040A0E3 ldrb r3, [r3, #24] @ zero_extendqisi2
297 029c 030000EA .LVL14:
298 .L56:
208:uartISR.c **** break;
209:uartISR.c ****
210:uartISR.c **** default: // Unknown
211:uartISR.c **** U1LSR;
299 156 0
300 02a0 5C309FE5 ldr r3, .L57+20
301 02a4 1420D3E5 .LVL15:
212:uartISR.c **** U1RBR;
302 rb r2, [r3, #8] @ zero_extendqisi2
303 02a8 0020D3E5 eor r3, r2, #1
304 ands r1, r3, #1
213:uartISR.c **** U1MSR;
305 e .L31
306 02ac 1830D3E5 ldr r3, .L57+8
307 str r4, [r3, #0]
308 ldr r3, .L57+12
309 strh r0, [r3, #0] @ movhi
310 02b0 4C309FE5 ldr r3, .L57+16
311 strh ip, [r3, #0] @ movhi
312 02b4 0820D3E5 .loc 1 218 0
313 02b8 013022E2 ldr r3, .L57+36
314 02bc 011013E2 str r1, [r3, #48]
315 02c0 BEFFFF1A .loc 1 219 0
316 02c4 2C309FE5 ldmfd sp!,{r1}
317 02c8 004083E5 msr spsr_c,r1
318 02cc 28309FE5 ldmfd sp!,{r0-r12,pc}^
319 02d0 B000C3E1 .loc 1 220 0
320 02d4 24309FE5 .L58:
321 02d8 B0C0C3E1 .align 2
214:uartISR.c **** break;
215:uartISR.c **** }
216:uartISR.c **** }
217:uartISR.c ****
218:uartISR.c **** VICVectAddr = 0x00000000; // clear this interrupt from the VIC
322 1_rx_extract_idx
323 02dc 30309FE5 .word uart1_tx_insert_idx
324 02e0 301083E5 .word uart1_tx_running
219:uartISR.c **** ISR_EXIT(); // recover registers and return
325 ord uart1_tx_extract_idx
326 02e4 0200BDE8 .word uart1_rx_insert_idx
327 02e8 01F061E1 .word -536805376
328 02ec FF9FFDE8 .word -2147483521
220:uartISR.c **** }
329 rd uart1_rx_buffer
330 .word uart1_tx_buffer
331 .word -4096
332 .LFE3:
334 02f4 00000000 .section .debug_frame,"",%progbits
335 02f8 00000000 .Lframe0:
336 02fc 00000000 .4byte .LECIE0-.LSCIE0
337 0300 00000000 .LSCIE0:
338 0304 000001E0 .4byte 0xffffffff
339 0308 7F000080 .byte 0x1
340 030c 00000000 .ascii "\000"
341 0310 00000000 .uleb128 0x1
342 0314 00F0FFFF .sleb128 -4
343 .byte 0xe
344 .byte 0xc
378 .byte 0x53
DEFINED SYMBOLS
*ABS*:00000000 uartISR.c
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/cccxaaaa.s:13 .text:00000000 uart0ISR
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/cccxaaaa.s:22 .text:00000000 $a
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/cccxaaaa.s:51 .text:00000050 $d
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/cccxaaaa.s:64 .text:0000007c $a
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/cccxaaaa.s:162 .text:0000015c $d
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/cccxaaaa.s:177 .text:00000184 uart1ISR
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/cccxaaaa.s:185 .text:00000184 $a
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/cccxaaaa.s:213 .text:000001d0 $d
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/cccxaaaa.s:228 .text:00000204 $a
C:\DOCUME~1\MINDAU~1\LOCALS~1\Temp/cccxaaaa.s:333 .text:000002f0 $d
UNDEFINED SYMBOLS
uart0_rx_extract_idx
uart0_tx_insert_idx
uart0_tx_running
uart0_tx_extract_idx
uart0_rx_insert_idx
uart0_rx_buffer
uart0_tx_buffer
uart1_rx_extract_idx
uart1_tx_insert_idx
uart1_tx_running
uart1_tx_extract_idx
uart1_rx_insert_idx
uart1_rx_buffer
uart1_tx_buffer
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