📄 uartisr.lst
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1 .file "uartISR.c"
9 .Ltext0:
10 .align 2
11 .global uart0ISR
13 uart0ISR:
14 .LFB2:
15 .file 1 "uartISR.c"
1:uartISR.c **** /******************************************************************************
2:uartISR.c **** *
3:uartISR.c **** * $RCSfile: $
4:uartISR.c **** * $Revision: $
5:uartISR.c **** *
6:uartISR.c **** * This module implements the ISRs for the UARTs on the LPC ARMs.
7:uartISR.c **** * Copyright 2004, R O SoftWare
8:uartISR.c **** * No guarantees, warrantees, or promises, implied or otherwise.
9:uartISR.c **** * May be used for hobby or commercial purposes provided copyright
10:uartISR.c **** * notice remains intact.
11:uartISR.c **** *
12:uartISR.c **** *****************************************************************************/
13:uartISR.c **** #include "types.h"
14:uartISR.c **** #include "LPC21xx.h"
15:uartISR.c **** #include "uart.h"
16:uartISR.c **** #include "uartISR.h"
17:uartISR.c **** #include "armVIC.h"
18:uartISR.c ****
19:uartISR.c ****
20:uartISR.c **** #if UART0_SUPPORT
21:uartISR.c ****
22:uartISR.c **** #ifdef UART0_RX_INT_MODE
23:uartISR.c **** extern uint8_t uart0_rx_buffer[UART0_RX_BUFFER_SIZE];
24:uartISR.c **** extern uint16_t uart0_rx_insert_idx, uart0_rx_extract_idx;
25:uartISR.c **** #endif // UART0_RX_INT_MODE
26:uartISR.c ****
27:uartISR.c **** #ifdef UART0_TX_INT_MODE
28:uartISR.c **** extern uint8_t uart0_tx_buffer[UART0_TX_BUFFER_SIZE];
29:uartISR.c **** extern uint16_t uart0_tx_insert_idx, uart0_tx_extract_idx;
30:uartISR.c **** extern int uart0_tx_running;
31:uartISR.c **** #endif // UART0_TX_INT_MODE
32:uartISR.c ****
33:uartISR.c **** #if defined(UART0_TX_INT_MODE) || defined(UART0_RX_INT_MODE)
34:uartISR.c **** /******************************************************************************
35:uartISR.c **** *
36:uartISR.c **** * Function Name: uart0ISR()
37:uartISR.c **** *
38:uartISR.c **** * Description:
39:uartISR.c **** * This function implements the ISR for UART0.
40:uartISR.c **** *
41:uartISR.c **** * Calling Sequence:
42:uartISR.c **** * void
43:uartISR.c **** *
44:uartISR.c **** * Returns:
45:uartISR.c **** * void
46:uartISR.c **** *
47:uartISR.c **** *****************************************************************************/
48:uartISR.c **** void uart0ISR(void)
49:uartISR.c **** {
16 Naked Function: prologue and epilogue provided by programmer.
17 @ args = 0, pretend = 0, frame = 0
18 @ frame_needed = 0, uses_anonymous_args = 0
19 .LVL0:
20 .loc 1 53 0
50:uartISR.c **** uint8_t iid;
51:uartISR.c ****
52:uartISR.c **** // perform proper ISR entry so thumb-interwork works properly
53:uartISR.c **** ISR_ENTRY();
21 lr, lr,#4
22 0000 04E04EE2 stmfd sp!,{r0-r12,lr}
23 0004 FF5F2DE9 mrs r1, spsr
24 0008 00104FE1 stmfd sp!,{r1}
25 000c 02002DE9 .LBB2:
26 .loc 1 77 0
54:uartISR.c ****
55:uartISR.c **** // loop until not more interrupt sources
56:uartISR.c **** while (((iid = U0IIR) & UIIR_NO_INT) == 0)
57:uartISR.c **** {
58:uartISR.c **** // identify & process the highest priority interrupt
59:uartISR.c **** switch (iid & UIIR_ID_MASK)
60:uartISR.c **** {
61:uartISR.c **** case UIIR_RLS_INT: // Receive Line Status
62:uartISR.c **** U0LSR; // read LSR to clear
63:uartISR.c **** break;
64:uartISR.c ****
65:uartISR.c **** #ifdef UART0_RX_INT_MODE
66:uartISR.c **** case UIIR_CTI_INT: // Character Timeout Indicator
67:uartISR.c **** case UIIR_RDA_INT: // Receive Data Available
68:uartISR.c **** do
69:uartISR.c **** {
70:uartISR.c **** uint16_t temp;
71:uartISR.c ****
72:uartISR.c **** // calc next insert index & store character
73:uartISR.c **** temp = (uart0_rx_insert_idx + 1) % UART0_RX_BUFFER_SIZE;
74:uartISR.c **** uart0_rx_buffer[uart0_rx_insert_idx] = U0RBR;
75:uartISR.c ****
76:uartISR.c **** // check for more room in queue
77:uartISR.c **** if (temp != uart0_rx_extract_idx)
27 3, .L27
28 0010 44319FE5 ldrh r6, [r3, #0]
29 0014 B060D3E1 .LBE2:
30 .loc 1 90 0
78:uartISR.c **** uart0_rx_insert_idx = temp; // update insert index
79:uartISR.c **** }
80:uartISR.c **** while (U0LSR & ULSR_RDR);
81:uartISR.c ****
82:uartISR.c **** break;
83:uartISR.c **** #endif
84:uartISR.c ****
85:uartISR.c **** #ifdef UART0_TX_INT_MODE
86:uartISR.c **** case UIIR_THRE_INT: // Transmit Holding Register Empty
87:uartISR.c **** while (U0LSR & ULSR_THRE)
88:uartISR.c **** {
89:uartISR.c **** // check if more data to send
90:uartISR.c **** if (uart0_tx_insert_idx != uart0_tx_extract_idx)
31 r3, .L27+4
32 0018 40319FE5 ldrh r5, [r3, #0]
33 001c B050D3E1 ldr r3, .L27+8
34 0020 3C319FE5 ldr r4, [r3, #0]
35 0024 004093E5 ldr r3, .L27+12
36 0028 38319FE5 ldrh r0, [r3, #0]
37 002c B000D3E1 ldr r3, .L27+16
38 0030 34319FE5 ldrh ip, [r3, #0]
39 0034 B0C0D3E1 .LVL1:
40 b .L26
41 0038 370000EA .L3:
42 .loc 1 59 0
43 and r3, r2, #14
44 003c 0E3002E2 sub r3, r3, #2
45 0040 023043E2 cmp r3, #10
46 0044 0A0053E3 ldrls pc, [pc, r3, asl #2]
47 0048 03F19F97 b .L4
48 004c 2F0000EA .p2align 2
49 .L8:
50 .word .L24
51 0050 F0000000 .word .L4
52 0054 10010000 .word .L21
53 0058 88000000 .word .L4
54 005c 10010000 .word .L7
55 0060 7C000000 .word .L4
56 0064 10010000 .word .L4
57 0068 10010000 .word .L4
58 006c 10010000 .word .L4
59 0070 10010000 .word .L4
60 0074 10010000 .word .L21
61 0078 88000000 .L7:
62 .loc 1 62 0
63 ldr r3, .L27+20
64 007c EC309FE5 ldrb r3, [r3, #20] @ zero_extendqisi2
65 0080 1430D3E5 b .L26
66 0084 240000EA .LVL2:
67 .L21:
68 .LBB3:
69 .loc 1 73 0
70 ldr r1, .L27+24
71 0088 E4109FE5 add r3, ip, #1
72 008c 01308CE2 .LVL3:
73 and r1, r3, r1
74 0090 011003E0 cmp r1, #0
75 0094 000051E3 .loc 1 74 0
76 ldr lr, .L27+20
77 0098 D0E09FE5 .loc 1 73 0
78 sublt r1, r1, #1
79 009c 011041B2 mvnlt r1, r1, asl #25
80 00a0 811CE0B1 .loc 1 74 0
81 ldrb r2, [lr, #0] @ zero_extendqisi2
82 00a4 0020DEE5 ldr r3, .L27+28
83 00a8 C8309FE5 .loc 1 73 0
84 mvnlt r1, r1, lsr #25
85 00ac A11CE0B1 .loc 1 74 0
86 strb r2, [ip, r3]
87 00b0 0320CCE7 .loc 1 73 0
88 addlt r1, r1, #1
89 00b4 011081B2 mov r3, r1, asl #16
90 00b8 0138A0E1 mov r3, r3, lsr #16
91 00bc 2338A0E1 .LVL4:
92 .LBE3:
93 .loc 1 80 0
94 ldrb r2, [lr, #20] @ zero_extendqisi2
95 00c0 1420DEE5 .LBB4:
96 .loc 1 77 0
97 cmp r3, r6
98 00c4 060053E1 movne ip, r3
99 00c8 03C0A011 .LBE4:
100 .loc 1 80 0
101 tst r2, #1
102 00cc 010012E3 beq .L26
103 00d0 1100000A b .L21
104 00d4 EBFFFFEA .LVL5:
105 .L12:
106 .loc 1 90 0
107 cmp r5, r0
108 00d8 000055E1 beq .L18
109 00dc 0900000A .loc 1 92 0
91:uartISR.c **** {
92:uartISR.c **** U0THR = uart0_tx_buffer[uart0_tx_extract_idx++];
110 1 93 0
111 00e0 94309FE5 and r0, r2, #127
112 00e4 0330D0E7 .L24:
113 00e8 0030C1E5 .loc 1 87 0
93:uartISR.c **** uart0_tx_extract_idx %= UART0_TX_BUFFER_SIZE;
114 r1, .L27+20
115 00ec 7F0002E2 ldrb r3, [r1, #20] @ zero_extendqisi2
116 tst r3, #32
117 .loc 1 93 0
118 00f0 78109FE5 add r2, r0, #1
119 00f4 1430D1E5 .loc 1 87 0
120 00f8 200013E3 bne .L12
121 b .L26
122 00fc 012080E2 .L18:
123 .loc 1 90 0
124 0100 F4FFFF1A mov r4, #0
125 0104 040000EA b .L26
126 .L4:
127 .loc 1 107 0
128 0108 0040A0E3 ldr r3, .L27+20
129 010c 020000EA ldrb r2, [r3, #20] @ zero_extendqisi2
130 .loc 1 108 0
94:uartISR.c **** }
95:uartISR.c **** else
96:uartISR.c **** {
97:uartISR.c **** // no
98:uartISR.c **** uart0_tx_running = 0; // clear running flag
99:uartISR.c **** break;
100:uartISR.c **** }
101:uartISR.c **** }
102:uartISR.c ****
103:uartISR.c **** break;
104:uartISR.c **** #endif // UART0_TX_INT_MODE
105:uartISR.c ****
106:uartISR.c **** default: // Unknown
107:uartISR.c **** U0LSR;
131 ] @ zero_extendqisi2
132 0110 58309FE5 .LVL6:
133 0114 1420D3E5 .L26:
108:uartISR.c **** U0RBR;
134 oc 1 56 0
135 0118 0030D3E5 ldr r3, .L27+20
136 .LVL7:
137 ldrb r2, [r3, #8] @ zero_extendqisi2
138 eor r3, r2, #1
139 011c 4C309FE5 ands r1, r3, #1
140 bne .L3
141 0120 0820D3E5 ldr r3, .L27+8
142 0124 013022E2 str r4, [r3, #0]
143 0128 011013E2 ldr r3, .L27+12
144 012c C2FFFF1A strh r0, [r3, #0] @ movhi
145 0130 2C309FE5 ldr r3, .L27+16
146 0134 004083E5 strh ip, [r3, #0] @ movhi
147 0138 28309FE5 .loc 1 113 0
148 013c B000C3E1 ldr r3, .L27+36
149 0140 24309FE5 str r1, [r3, #48]
150 0144 B0C0C3E1 .loc 1 114 0
109:uartISR.c **** break;
110:uartISR.c **** }
111:uartISR.c **** }
112:uartISR.c ****
113:uartISR.c **** VICVectAddr = 0x00000000; // clear this interrupt from the VIC
151 msr spsr_c,r1
152 0148 30309FE5 ldmfd sp!,{r0-r12,pc}^
153 014c 301083E5 .loc 1 115 0
114:uartISR.c **** ISR_EXIT(); // recover registers and return
154 8:
155 0150 0200BDE8 .align 2
156 0154 01F061E1 .L27:
157 0158 FF9FFDE8 .word uart0_rx_extract_idx
115:uartISR.c **** }
158 rd uart0_tx_insert_idx
159 .word uart0_tx_running
160 .word uart0_tx_extract_idx
161 .word uart0_rx_insert_idx
162 015c 00000000 .word -536821760
163 0160 00000000 .word -2147483521
164 0164 00000000 .word uart0_rx_buffer
165 0168 00000000 .word uart0_tx_buffer
166 016c 00000000 .word -4096
167 0170 00C000E0 .LFE2:
169 0178 00000000 .align 2
170 017c 00000000 .global uart1ISR
172 uart1ISR:
173 .LFB3:
174 .loc 1 149 0
175 @ Naked Function: prologue and epilogue provided by programmer.
176 @ args = 0, pretend = 0, frame = 0
177 @ frame_needed = 0, uses_anonymous_args = 0
178 .LVL8:
116:uartISR.c **** #endif // defined(UART0_TX_INT_MODE) || defined(UART0_RX_INT_MODE)
117:uartISR.c **** #endif // UART0_SUPPORT
118:uartISR.c ****
119:uartISR.c ****
120:uartISR.c **** #if UART1_SUPPORT
121:uartISR.c ****
122:uartISR.c **** #ifdef UART1_RX_INT_MODE
123:uartISR.c **** extern uint8_t uart1_rx_buffer[UART1_RX_BUFFER_SIZE];
124:uartISR.c **** extern uint16_t uart1_rx_insert_idx, uart1_rx_extract_idx;
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