main.lss

rtc code for lpc2148

#endif
  return (uint8_t)ch;
 860:	e20430ff 	and	r3, r4, #255	; 0xff
}
 864:	e1a00003 	mov	r0, r3
 868:	e8bd80f0 	ldmia	sp!, {r4, r5, r6, r7, pc}
 86c:	4000008e 	andmi	r0, r0, lr, lsl #1
 870:	8000007f 	andhi	r0, r0, pc, ror r0
 874:	40000198 	mulmi	r0, r8, r1
 878:	e000c000 	and	ip, r0, r0
 87c:	400001a0 	andmi	r0, r0, r0, lsr #3
 880:	4000000c 	andmi	r0, r0, ip

00000884 <uart0Space>:

/******************************************************************************
 *
 * Function Name: uart0Space()
 *
 * Description:  
 *    This function gets the available space in the transmit queue
 *
 * Calling Sequence: 
 *    void
 *
 * Returns:
 *    available space in the transmit queue
 *
 *****************************************************************************/
uint16_t uart0Space(void)
{
#ifdef UART0_TX_INT_MODE
  int space;

  if ((space = (uart0_tx_extract_idx - uart0_tx_insert_idx)) <= 0)
 884:	e59f3024 	ldr	r3, [pc, #36]	; 8b0 <.text+0x8b0>
 888:	e1d320b0 	ldrh	r2, [r3]
 88c:	e59f3020 	ldr	r3, [pc, #32]	; 8b4 <.text+0x8b4>
 890:	e1d330b0 	ldrh	r3, [r3]
 894:	e0630002 	rsb	r0, r3, r2
 898:	e3500000 	cmp	r0, #0	; 0x0
    space += UART0_TX_BUFFER_SIZE;
 89c:	d2800080 	addle	r0, r0, #128	; 0x80
 8a0:	e2400001 	sub	r0, r0, #1	; 0x1
 8a4:	e1a00800 	mov	r0, r0, lsl #16

  return (uint16_t)(space - 1);
#else
  return USHRT_MAX;
#endif
}
 8a8:	e1a00820 	mov	r0, r0, lsr #16
 8ac:	e12fff1e 	bx	lr
 8b0:	40000198 	mulmi	r0, r8, r1
 8b4:	4000008e 	andmi	r0, r0, lr, lsl #1

000008b8 <uart0Puts>:

/******************************************************************************
 *
 * Function Name: uart0Puts()
 *
 * Description:  
 *    This function writes a NULL terminated 'string' to the UART output
 *    queue, returning a pointer to the next character to be written.
 *
 * Calling Sequence: 
 *    address of the string
 *
 * Returns:
 *    a pointer to the next character to be written
 *    (\0 if full string is written)
 *
 *****************************************************************************/
const char *uart0Puts(const char *string)
{
 8b8:	e92d4010 	stmdb	sp!, {r4, lr}
 8bc:	e1a04000 	mov	r4, r0
 8c0:	ea000000 	b	8c8 <uart0Puts+0x10>
  register char ch;

  while ((ch = *string) && (uart0Putch(ch) >= 0))
    string++;
 8c4:	e2844001 	add	r4, r4, #1	; 0x1
 8c8:	e5d43000 	ldrb	r3, [r4]
 8cc:	e2530000 	subs	r0, r3, #0	; 0x0
 8d0:	0a000002 	beq	8e0 <uart0Puts+0x28>
 8d4:	ebffffbc 	bl	7cc <uart0Putch>
 8d8:	e3500000 	cmp	r0, #0	; 0x0
 8dc:	aafffff8 	bge	8c4 <uart0Puts+0xc>

  return string;
}
 8e0:	e1a00004 	mov	r0, r4
 8e4:	e8bd8010 	ldmia	sp!, {r4, pc}

000008e8 <uart0Write>:

/******************************************************************************
 *
 * Function Name: uart0Write()
 *
 * Description:  
 *    This function writes 'count' characters from 'buffer' to the UART
 *    output queue.
 *
 * Calling Sequence: 
 *    
 *
 * Returns:
 *    0 on success, -1 if insufficient room, -2 on error
 *    NOTE: if insufficient room, no characters are written.
 *
 *****************************************************************************/
int uart0Write(const char *buffer, uint16_t count)
{
 8e8:	e92d4070 	stmdb	sp!, {r4, r5, r6, lr}
 8ec:	e1a01801 	mov	r1, r1, lsl #16
 8f0:	e1a06821 	mov	r6, r1, lsr #16
 8f4:	e1a05000 	mov	r5, r0
#ifdef UART0_TX_INT_MODE
  if (count > uart0Space())
 8f8:	ebffffe1 	bl	884 <uart0Space>
 8fc:	e1560000 	cmp	r6, r0
 900:	83e00000 	mvnhi	r0, #0	; 0x0
 904:	88bd8070 	ldmhiia	sp!, {r4, r5, r6, pc}
 908:	ea000001 	b	914 <uart0Write+0x2c>
    return -1;
#endif
  while (count && (uart0Putch(*buffer++) >= 0))
 90c:	e3a00000 	mov	r0, #0	; 0x0
 910:	e8bd8070 	ldmia	sp!, {r4, r5, r6, pc}
 914:	e1a04006 	mov	r4, r6
 918:	ea000002 	b	928 <uart0Write+0x40>
    count--;
 91c:	e2443001 	sub	r3, r4, #1	; 0x1
 920:	e1a03803 	mov	r3, r3, lsl #16
 924:	e1a04823 	mov	r4, r3, lsr #16
 928:	e3540000 	cmp	r4, #0	; 0x0
 92c:	0afffff6 	beq	90c <uart0Write+0x24>
 930:	e4d50001 	ldrb	r0, [r5], #1
 934:	ebffffa4 	bl	7cc <uart0Putch>
 938:	e3500000 	cmp	r0, #0	; 0x0
 93c:	aafffff6 	bge	91c <uart0Write+0x34>
 940:	e3e00001 	mvn	r0, #1	; 0x1

  return (count ? -2 : 0);
}
 944:	e8bd8070 	ldmia	sp!, {r4, r5, r6, pc}

00000948 <uart0TxEmpty>:

/******************************************************************************
 *
 * Function Name: uart0TxEmpty()
 *
 * Description:
 *    This function returns the status of the UART transmit data
 *    registers.
 *
 * Calling Sequence: 
 *    void
 *
 * Returns:
 *    FALSE - either the tx holding or shift register is not empty
 *   !FALSE - if both the tx holding & shift registers are empty
 *
 *****************************************************************************/
int uart0TxEmpty(void)
{
  return (U0LSR & (ULSR_THRE | ULSR_TEMT)) == (ULSR_THRE | ULSR_TEMT);
 948:	e59f3014 	ldr	r3, [pc, #20]	; 964 <.text+0x964>
 94c:	e5d30014 	ldrb	r0, [r3, #20]
 950:	e2000060 	and	r0, r0, #96	; 0x60
}
 954:	e3500060 	cmp	r0, #96	; 0x60
 958:	13a00000 	movne	r0, #0	; 0x0
 95c:	03a00001 	moveq	r0, #1	; 0x1
 960:	e12fff1e 	bx	lr
 964:	e000c000 	and	ip, r0, r0

00000968 <uart0TxFlush>:

/******************************************************************************
 *
 * Function Name: uart0TxFlush()
 *
 * Description:  
 *    This function removes all characters from the UART transmit queue
 *    (without transmitting them).
 *
 * Calling Sequence: 
 *    void
 *
 * Returns:
 *    void
 *
 *****************************************************************************/
void uart0TxFlush(void)
{
 968:	e92d4010 	stmdb	sp!, {r4, lr}
#ifdef UART0_TX_INT_MODE
  unsigned cpsr;

  U0FCR |= UFCR_TX_FIFO_RESET;          // clear the TX fifo
 96c:	e59f4034 	ldr	r4, [pc, #52]	; 9a8 <.text+0x9a8>
 970:	e5d43008 	ldrb	r3, [r4, #8]
 974:	e3833004 	orr	r3, r3, #4	; 0x4
 978:	e5c43008 	strb	r3, [r4, #8]

  // "Empty" the transmit buffer.
  cpsr = disableIRQ();                  // disable global interrupts
 97c:	ebfffeb8 	bl	464 <disableIRQ>
  U0IER &= ~UIER_ETBEI;                 // disable TX interrupts
 980:	e5d43004 	ldrb	r3, [r4, #4]
 984:	e20330fd 	and	r3, r3, #253	; 0xfd
 988:	e5c43004 	strb	r3, [r4, #4]
  restoreIRQ(cpsr);                     // restore global interrupts
 98c:	ebfffeb8 	bl	474 <restoreIRQ>
  uart0_tx_insert_idx = uart0_tx_extract_idx = 0;
 990:	e59f3014 	ldr	r3, [pc, #20]	; 9ac <.text+0x9ac>
 994:	e3a02000 	mov	r2, #0	; 0x0
 998:	e1c320b0 	strh	r2, [r3]
 99c:	e59f300c 	ldr	r3, [pc, #12]	; 9b0 <.text+0x9b0>
 9a0:	e1c320b0 	strh	r2, [r3]
#else
  U0FCR |= UFCR_TX_FIFO_RESET;          // clear the TX fifo
#endif
}
 9a4:	e8bd8010 	ldmia	sp!, {r4, pc}
 9a8:	e000c000 	and	ip, r0, r0
 9ac:	4000008e 	andmi	r0, r0, lr, lsl #1
 9b0:	40000198 	mulmi	r0, r8, r1

000009b4 <uart0Getch>:

/******************************************************************************
 *
 * Function Name: uart0Getch()
 *
 * Description:  
 *    This function gets a character from the UART receive queue
 *
 * Calling Sequence: 
 *    void
 *
 * Returns:
 *    character on success, -1 if no character is available
 *
 *****************************************************************************/
int uart0Getch(void)
{
 9b4:	e52de004 	str	lr, [sp, #-4]!
#ifdef UART0_RX_INT_MODE
  uint8_t ch;

  if (uart0_rx_insert_idx == uart0_rx_extract_idx) // check if character is available
 9b8:	e59fe034 	ldr	lr, [pc, #52]	; 9f4 <.text+0x9f4>
 9bc:	e1de30b0 	ldrh	r3, [lr]
 9c0:	e1a0c803 	mov	ip, r3, lsl #16
 9c4:	e59f302c 	ldr	r3, [pc, #44]	; 9f8 <.text+0x9f8>
 9c8:	e1a0282c 	mov	r2, ip, lsr #16
 9cc:	e1d310b0 	ldrh	r1, [r3]
    return -1;

  ch = uart0_rx_buffer[uart0_rx_extract_idx++]; // get character, bump pointer
 9d0:	e2823001 	add	r3, r2, #1	; 0x1
  uart0_rx_extract_idx %= UART0_RX_BUFFER_SIZE; // limit the pointer
 9d4:	e203307f 	and	r3, r3, #127	; 0x7f
 9d8:	e1510002 	cmp	r1, r2
 9dc:	11ce30b0 	strneh	r3, [lr]
 9e0:	159f3014 	ldrne	r3, [pc, #20]	; 9fc <.text+0x9fc>
 9e4:	17d3382c 	ldrneb	r3, [r3, ip, lsr #16]
 9e8:	e3e00000 	mvn	r0, #0	; 0x0
  return ch;
 9ec:	11a00003 	movne	r0, r3
#else
  if (U0LSR & ULSR_RDR)                 // check if character is available
    return U0RBR;                       // return character

  return -1;
#endif
}
 9f0:	e49df004 	ldr	pc, [sp], #4
 9f4:	40000226 	andmi	r0, r0, r6, lsr #4
 9f8:	40000190 	mulmi	r0, r0, r1
 9fc:	400001a4 	andmi	r0, r0, r4, lsr #3

00000a00 <uart1Init>:

#endif


#if UART1_SUPPORT

/******************************************************************************
 *
 * Function Name: uart1Init()
 *
 * Description:  
 *    This function initializes the UART for async mode
 *
 * Calling Sequence: 
 *    baudrate divisor - use UART_BAUD macro
 *    mode - see typical modes (uart.h)
 *    fmode - see typical fmodes (uart.h)
 *
 * Returns:
 *    void
 *
 * NOTE: uart1Init(UART_BAUD(9600), UART_8N1, UART_FIFO_8);
 *
 *****************************************************************************/
void uart1Init(uint16_t baud, uint8_t mode, uint8_t fmode)
{
 a00:	e92d4010 	stmdb	sp!, {r4, lr}
  // set port pins for UART1
  PINSEL0 = (PINSEL0 & ~U1_PINMASK) | U1_PINSEL;
 a04:	e59fe0b4 	ldr	lr, [pc, #180]	; ac0 <.text+0xac0>
 a08:	e59e3000 	ldr	r3, [lr]

  U1IER = 0x00;                         // disable all interrupts
 a0c:	e59fc0b0 	ldr	ip, [pc, #176]	; ac4 <.text+0xac4>
 a10:	e3c3380f 	bic	r3, r3, #983040	; 0xf0000
 a14:	e3a04000 	mov	r4, #0	; 0x0
 a18:	e3833805 	orr	r3, r3, #327680	; 0x50000
 a1c:	e58e3000 	str	r3, [lr]
 a20:	e1a00800 	mov	r0, r0, lsl #16
 a24:	e5cc4004 	strb	r4, [ip, #4]
 a28:	e1a0e820 	mov	lr, r0, lsr #16
  U1IIR;                                // clear interrupt ID
 a2c:	e5dc3008 	ldrb	r3, [ip, #8]
 a30:	e20220ff 	and	r2, r2, #255	; 0xff
  U1RBR;                                // clear receive register
 a34:	e5dc3000 	ldrb	r3, [ip]
  U1LSR;                                // clear line status register

  // set the baudrate
  U1LCR = ULCR_DLAB_ENABLE;             // select divisor latches 
  U1DLL = (uint8_t)baud;                // set for baud low byte
 a38:	e20ee0ff 	and	lr, lr, #255	; 0xff
 a3c:	e5dc3014 	ldrb	r3, [ip, #20]
  U1DLM = (uint8_t)(baud >> 8);         // set for baud high byte
 a40:	e1a00c20 	mov	r0, r0, lsr #24
 a44:	e3e0307f 	mvn	r3, #127	; 0x7f

  // set the number of characters and other
  // user specified operating parameters
  U1LCR = (mode & ~ULCR_DLAB_ENABLE);
 a48:	e201107f 	and	r1, r1, #127	; 0x7f
 a4c:	e5cc300c 	strb	r3, [ip, #12]
 a50:	e5cce000 	strb	lr, [ip]
 a54:	e5cc0004 	strb	r0, [ip, #4]
 a58:	e5cc100c 	strb	r1, [ip, #12]
  U1FCR = fmode;
 a5c:	e5cc2008 	strb	r2, [ip, #8]

#if defined(UART1_TX_INT_MODE) || defined(UART1_RX_INT_MODE)
  // initialize the interrupt vector
  VICIntSelect &= ~VIC_BIT(VIC_UART1);  // UART1 selected as IRQ
 a60:	e59f2060 	ldr	r2, [pc, #96]	; ac8 <.text+0xac8>
 a64:	e592300c 	ldr	r3, [r2, #12]
 a68:	e3c33080 	bic	r3, r3, #128	; 0x80
 a6c:	e582300c 	str	r3, [r2, #12]
  VICIntEnable = VIC_BIT(VIC_UART1);    // UART1 interrupt enabled
 a70:	e3a03080 	mov	r3, #128	; 0x80
 a74:	e5823010 	str	r3, [r2, #16]
  VICVectCntl1 = VIC_ENABLE | VIC_UART1;
 a78:	e3a03027 	mov	r3, #39	; 0x27
 a7c:	e5823204 	str	r3, [r2, #516]
  VICVectAddr1 = (uint32_t)uart1ISR;    // address of the ISR
 a80:	e59f3044 	ldr	r3, [pc, #68]	; acc <.text+0xacc>
 a84:	e5823104 	str	r3, [r2, #260]

#ifdef UART1_TX_INT_MODE
  uart1_tx_extract_idx = uart1_tx_insert_idx = 0;
  uart1_tx_running = 0;
#endif

#ifdef UART1_RX_INT_MODE
  // initialize data queues
  uart1_rx_extract_idx = uart1_rx_insert_idx = 0;

  // enable receiver interrupts
  U1IER |= UIER_ERBFI;
 a88:	e5dc3004 	ldrb	r3, [ip, #4]
 a8c:	e59f203c 	ldr	r2, [pc, #60]	; ad0 <.text+0xad0>
 a90:	e3833001 	orr	r3, r3, #1	; 0x1
 a94:	e1c240b0 	strh	r4, [r2]
 a98:	e5cc3004 	strb	r3, [ip, #4]
 a9c:	e59f3030 	ldr	r3, [pc, #48]	; ad4 <.text+0xad4>
 aa0:	e1c340b0 	strh	r4, [r3]
 aa4:	e59f302c 	ldr	r3, [pc, #44]	; ad8 <.text+0xad8>
 aa8:	e1c340b0 	strh	r4, [r3]
 aac:	e59f3028 	ldr	r3, [pc, #40]	; adc <.text+0xadc>
 ab0:	e5834000 	str	r4, [r3]
 ab4:	e59f3024 	ldr	r3, [pc, #36]	; ae0 <.text+0xae0>
 ab8:	e1c340b0 	strh	r4, [r3]
#endif
#endif
}