main.lss

rtc code for lpc2148

{
 4cc:	e24ee004 	sub	lr, lr, #4	; 0x4
 4d0:	e92d501f 	stmdb	sp!, {r0, r1, r2, r3, r4, ip, lr}
   if (time_toggle==0)
 4d4:	e59f4054 	ldr	r4, [pc, #84]	; 530 <.text+0x530>
 4d8:	e5943000 	ldr	r3, [r4]
 4dc:	e3530000 	cmp	r3, #0	; 0x0
   {
	uart0Puts("\n\rTic\r\n");//Tic Tac output to UART0
 4e0:	e59f004c 	ldr	r0, [pc, #76]	; 534 <.text+0x534>
 4e4:	1a000002 	bne	4f4 <rtc0+0x28>
 4e8:	eb0000f2 	bl	8b8 <uart0Puts>
	time_toggle=1;
 4ec:	e3a03001 	mov	r3, #1	; 0x1
 4f0:	ea000002 	b	500 <rtc0+0x34>
   }
   else
   {
	uart0Puts("\n\rTac\r\n");
 4f4:	e59f003c 	ldr	r0, [pc, #60]	; 538 <.text+0x538>
 4f8:	eb0000ee 	bl	8b8 <uart0Puts>
	time_toggle=0;
 4fc:	e3a03000 	mov	r3, #0	; 0x0
 500:	e5843000 	str	r3, [r4]
	}
   ILR |= 1;     // Clear interrupt flag
 504:	e59f2030 	ldr	r2, [pc, #48]	; 53c <.text+0x53c>
 508:	e5923000 	ldr	r3, [r2]
 50c:	e3833001 	orr	r3, r3, #1	; 0x1
 510:	e5823000 	str	r3, [r2]
   VICVectAddr = 0;     // Acknowledge Interrupt
 514:	e59f3024 	ldr	r3, [pc, #36]	; 540 <.text+0x540>
 518:	e3a02000 	mov	r2, #0	; 0x0
 51c:	e5832030 	str	r2, [r3, #48]
   PCON = 1;     // IDLE mode
 520:	e59f301c 	ldr	r3, [pc, #28]	; 544 <.text+0x544>
 524:	e2822001 	add	r2, r2, #1	; 0x1
 528:	e5c320c0 	strb	r2, [r3, #192]
} 
 52c:	e8fd901f 	ldmia	sp!, {r0, r1, r2, r3, r4, ip, pc}^
 530:	40000000 	andmi	r0, r0, r0
 534:	00000e1c 	andeq	r0, r0, ip, lsl lr
 538:	00000e24 	andeq	r0, r0, r4, lsr #28
 53c:	e0024000 	and	r4, r2, r0
 540:	fffff000 	undefined instruction 0xfffff000
 544:	e01fc000 	ands	ip, pc, r0

00000548 <init_rtc>:
void init_rtc(void)
{
   ILR = 3;     // Disable 32'768 interrupt
 548:	e59f3038 	ldr	r3, [pc, #56]	; 588 <.text+0x588>
 54c:	e3a02003 	mov	r2, #3	; 0x3
 550:	e5832000 	str	r2, [r3]
   CCR = 0x11;     // Clock enable + 32'767Hz quartz enable
 554:	e282200e 	add	r2, r2, #14	; 0xe
 558:	e2833008 	add	r3, r3, #8	; 0x8
 55c:	e4832004 	str	r2, [r3], #4
   CIIR = 0x01;     // Interupt every second
 560:	e3a02001 	mov	r2, #1	; 0x1
 564:	e5832000 	str	r2, [r3]
   VICVectAddr1 = (unsigned long)rtc0;     // set interrupt vector in 1
 568:	e59f101c 	ldr	r1, [pc, #28]	; 58c <.text+0x58c>
 56c:	e59f301c 	ldr	r3, [pc, #28]	; 590 <.text+0x590>
 570:	e5813104 	str	r3, [r1, #260]
   VICVectCntl1 = 0x0000002D;     // use it for RTC Interrupt
 574:	e3a0302d 	mov	r3, #45	; 0x2d
 578:	e5813204 	str	r3, [r1, #516]
   VICIntEnable = 0x00002000;     // Enable RTC Interrupt
 57c:	e3a03a02 	mov	r3, #8192	; 0x2000
 580:	e5813010 	str	r3, [r1, #16]
}       
 584:	e12fff1e 	bx	lr
 588:	e0024000 	and	r4, r2, r0
 58c:	fffff000 	undefined instruction 0xfffff000
 590:	000004cc 	andeq	r0, r0, ip, asr #9

00000594 <set_time>:
void set_time(void)
{
   YEAR = 2006;     // Year
 594:	e59f2054 	ldr	r2, [pc, #84]	; 5f0 <.text+0x5f0>
 598:	e59f3054 	ldr	r3, [pc, #84]	; 5f4 <.text+0x5f4>
 59c:	e5832000 	str	r2, [r3]
   MONTH = 5;     // Month
 5a0:	e3a02005 	mov	r2, #5	; 0x5
 5a4:	e2433004 	sub	r3, r3, #4	; 0x4
 5a8:	e5832000 	str	r2, [r3]
   DOM = 23;     // Day of month
 5ac:	e3a01017 	mov	r1, #23	; 0x17
 5b0:	e243300c 	sub	r3, r3, #12	; 0xc
 5b4:	e5831000 	str	r1, [r3]
   DOY = 38;     // Day of year
 5b8:	e2822021 	add	r2, r2, #33	; 0x21
 5bc:	e2833008 	add	r3, r3, #8	; 0x8
 5c0:	e5832000 	str	r2, [r3]
   DOW = 143;     // Day of week
 5c4:	e2822069 	add	r2, r2, #105	; 0x69
 5c8:	e2433004 	sub	r3, r3, #4	; 0x4
 5cc:	e4032008 	str	r2, [r3], #-8
   HOUR = 23;     // Hours
 5d0:	e5831000 	str	r1, [r3]
   MIN = 14;     // Minutes
 5d4:	e3a0200e 	mov	r2, #14	; 0xe
 5d8:	e2433004 	sub	r3, r3, #4	; 0x4
 5dc:	e5832000 	str	r2, [r3]
   SEC = 30;     // Seconds
 5e0:	e2822010 	add	r2, r2, #16	; 0x10
 5e4:	e2433004 	sub	r3, r3, #4	; 0x4
 5e8:	e5832000 	str	r2, [r3]
}
 5ec:	e12fff1e 	bx	lr
 5f0:	000007d6 	ldreqd	r0, [r0], -r6
 5f4:	e002403c 	and	r4, r2, ip, lsr r0

000005f8 <main>:
 5f8:	e59f20d4 	ldr	r2, [pc, #212]	; 6d4 <.text+0x6d4>
 5fc:	e3a03024 	mov	r3, #36	; 0x24

/******************************************************************************
 *
 * Function Name: main()
 *
 * Description:
 *    This function is the program entry point.  After initializing the
 *    system, it sends a greeting out UART0 then enters an endless loop
 *    echoing chracters on the UART and blinking an LED every half
 *    second.
 *
 * Calling Sequence: 
 *    void
 *
 * Returns:
 *    void
 *
 *****************************************************************************/
int main(void)
{
 600:	e92d4010 	stmdb	sp!, {r4, lr}
 604:	e5c23084 	strb	r3, [r2, #132]
 608:	e3a03001 	mov	r3, #1	; 0x1
 60c:	e5c23080 	strb	r3, [r2, #128]
 610:	e59f10c0 	ldr	r1, [pc, #192]	; 6d8 <.text+0x6d8>
 614:	e59f00c0 	ldr	r0, [pc, #192]	; 6dc <.text+0x6dc>
 618:	e3e03055 	mvn	r3, #85	; 0x55
 61c:	e5c2308c 	strb	r3, [r2, #140]
 620:	e3a0c000 	mov	ip, #0	; 0x0
 624:	e3e0e000 	mvn	lr, #0	; 0x0
 628:	e28330ab 	add	r3, r3, #171	; 0xab
 62c:	e5c2308c 	strb	r3, [r2, #140]
 630:	e581000c 	str	r0, [r1, #12]
 634:	e581c004 	str	ip, [r1, #4]
 638:	e5810008 	str	r0, [r1, #8]
 63c:	e581e01c 	str	lr, [r1, #28]
 640:	e581c014 	str	ip, [r1, #20]
 644:	e581e018 	str	lr, [r1, #24]
 648:	e59f0084 	ldr	r0, [pc, #132]	; 6d4 <.text+0x6d4>
 64c:	e1d038b8 	ldrh	r3, [r0, #136]
 650:	e3130b01 	tst	r3, #1024	; 0x400
 654:	0afffffb 	beq	648 <main+0x50>
 658:	e3a04003 	mov	r4, #3	; 0x3
 65c:	e3e03055 	mvn	r3, #85	; 0x55
 660:	e5c04080 	strb	r4, [r0, #128]
 664:	e5c0308c 	strb	r3, [r0, #140]
 668:	e28330ab 	add	r3, r3, #171	; 0xab
 66c:	e5c0308c 	strb	r3, [r0, #140]
 670:	e59f2068 	ldr	r2, [pc, #104]	; 6e0 <.text+0x6e0>
 674:	e3a01002 	mov	r1, #2	; 0x2
 678:	e3a03001 	mov	r3, #1	; 0x1
 67c:	e5c04004 	strb	r4, [r0, #4]
 680:	e5c01000 	strb	r1, [r0]
 684:	e5c01100 	strb	r1, [r0, #256]
 688:	e5c03040 	strb	r3, [r0, #64]
 68c:	e3e03000 	mvn	r3, #0	; 0x0
 690:	e5823014 	str	r3, [r2, #20]
 694:	e2833001 	add	r3, r3, #1	; 0x1
 698:	e582300c 	str	r3, [r2, #12]
 69c:	e59f3040 	ldr	r3, [pc, #64]	; 6e4 <.text+0x6e4>
 6a0:	e5823034 	str	r3, [r2, #52]
 6a4:	eb00019b 	bl	d18 <initSysTime>
 6a8:	e1a01004 	mov	r1, r4
 6ac:	e3a02081 	mov	r2, #129	; 0x81
 6b0:	e3a00010 	mov	r0, #16	; 0x10
 6b4:	eb00000c 	bl	6ec <uart0Init>
	uint32_t startTime;
	sysInit();
#if defined(UART0_TX_INT_MODE) || defined(UART0_RX_INT_MODE) 
	enableIRQ();
 6b8:	ebffff74 	bl	490 <enableIRQ>
#endif
uart0Puts("\n\rRTC interupts every second\r\n");
 6bc:	e59f0024 	ldr	r0, [pc, #36]	; 6e8 <.text+0x6e8>
 6c0:	eb00007c 	bl	8b8 <uart0Puts>
startTime = getSysTICs();
 6c4:	eb0001a2 	bl	d54 <getSysTICs>
init_rtc();
 6c8:	ebffff9e 	bl	548 <init_rtc>
set_time();
 6cc:	ebffffb0 	bl	594 <set_time>
 6d0:	eafffffe 	b	6d0 <main+0xd8>
 6d4:	e01fc000 	ands	ip, pc, r0
 6d8:	e0028000 	and	r8, r2, r0
 6dc:	ffffa4fc 	undefined instruction 0xffffa4fc
 6e0:	fffff000 	undefined instruction 0xfffff000
 6e4:	00000114 	andeq	r0, r0, r4, lsl r1
 6e8:	00000e2c 	andeq	r0, r0, ip, lsr #28

000006ec <uart0Init>:
 * NOTE: uart0Init(UART_BAUD(9600), UART_8N1, UART_FIFO_8);
 *
 *****************************************************************************/
void uart0Init(uint16_t baud, uint8_t mode, uint8_t fmode)
{
 6ec:	e92d4010 	stmdb	sp!, {r4, lr}
  // set port pins for UART0
  PINSEL0 = (PINSEL0 & ~U0_PINMASK) | U0_PINSEL;
 6f0:	e59fe0b0 	ldr	lr, [pc, #176]	; 7a8 <.text+0x7a8>
 6f4:	e59e3000 	ldr	r3, [lr]

  U0IER = 0x00;                         // disable all interrupts
 6f8:	e59fc0ac 	ldr	ip, [pc, #172]	; 7ac <.text+0x7ac>
 6fc:	e3c3300f 	bic	r3, r3, #15	; 0xf
 700:	e3a04000 	mov	r4, #0	; 0x0
 704:	e3833005 	orr	r3, r3, #5	; 0x5
 708:	e58e3000 	str	r3, [lr]
 70c:	e1a00800 	mov	r0, r0, lsl #16
 710:	e5cc4004 	strb	r4, [ip, #4]
 714:	e1a0e820 	mov	lr, r0, lsr #16
  U0IIR;                                // clear interrupt ID
 718:	e5dc3008 	ldrb	r3, [ip, #8]
 71c:	e20220ff 	and	r2, r2, #255	; 0xff
  U0RBR;                                // clear receive register
 720:	e5dc3000 	ldrb	r3, [ip]
  U0LSR;                                // clear line status register

  // set the baudrate
  U0LCR = ULCR_DLAB_ENABLE;             // select divisor latches 
  U0DLL = (uint8_t)baud;                // set for baud low byte
  U0DLM = (uint8_t)(baud >> 8);         // set for baud high byte

  // set the number of characters and other
  // user specified operating parameters
  U0LCR = (mode & ~ULCR_DLAB_ENABLE);
 724:	e201107f 	and	r1, r1, #127	; 0x7f
 728:	e5dc3014 	ldrb	r3, [ip, #20]
 72c:	e20ee0ff 	and	lr, lr, #255	; 0xff
 730:	e3e0307f 	mvn	r3, #127	; 0x7f
 734:	e1a00c20 	mov	r0, r0, lsr #24
 738:	e5cc300c 	strb	r3, [ip, #12]
 73c:	e5cce000 	strb	lr, [ip]
 740:	e5cc0004 	strb	r0, [ip, #4]
 744:	e5cc100c 	strb	r1, [ip, #12]
  U0FCR = fmode;
 748:	e5cc2008 	strb	r2, [ip, #8]

#if defined(UART0_TX_INT_MODE) || defined(UART0_RX_INT_MODE)
  // initialize the interrupt vector
  VICIntSelect &= ~VIC_BIT(VIC_UART0);  // UART0 selected as IRQ
 74c:	e59f105c 	ldr	r1, [pc, #92]	; 7b0 <.text+0x7b0>
 750:	e591300c 	ldr	r3, [r1, #12]
 754:	e3c33040 	bic	r3, r3, #64	; 0x40
 758:	e581300c 	str	r3, [r1, #12]
  VICIntEnable = VIC_BIT(VIC_UART0);    // UART0 interrupt enabled
  VICVectCntl0 = VIC_ENABLE | VIC_UART0;
  VICVectAddr0 = (uint32_t)uart0ISR;    // address of the ISR

#ifdef UART0_TX_INT_MODE
  // initialize the transmit data queue
  uart0_tx_extract_idx = uart0_tx_insert_idx = 0;
 75c:	e59f3050 	ldr	r3, [pc, #80]	; 7b4 <.text+0x7b4>
 760:	e1c340b0 	strh	r4, [r3]
 764:	e3a03040 	mov	r3, #64	; 0x40
 768:	e5813010 	str	r3, [r1, #16]
 76c:	e59f3044 	ldr	r3, [pc, #68]	; 7b8 <.text+0x7b8>
 770:	e1c340b0 	strh	r4, [r3]
 774:	e3a03026 	mov	r3, #38	; 0x26
 778:	e5813200 	str	r3, [r1, #512]
 77c:	e59f3038 	ldr	r3, [pc, #56]	; 7bc <.text+0x7bc>
  uart0_tx_running = 0;
#endif

#ifdef UART0_RX_INT_MODE
  // initialize the receive data queue
  uart0_rx_extract_idx = uart0_rx_insert_idx = 0;
 780:	e59f2038 	ldr	r2, [pc, #56]	; 7c0 <.text+0x7c0>
 784:	e5813100 	str	r3, [r1, #256]

  // enable receiver interrupts
  U0IER = UIER_ERBFI;
 788:	e3a03001 	mov	r3, #1	; 0x1
 78c:	e1c240b0 	strh	r4, [r2]
 790:	e5cc3004 	strb	r3, [ip, #4]
 794:	e59f3028 	ldr	r3, [pc, #40]	; 7c4 <.text+0x7c4>
 798:	e5834000 	str	r4, [r3]
 79c:	e59f3024 	ldr	r3, [pc, #36]	; 7c8 <.text+0x7c8>
 7a0:	e1c340b0 	strh	r4, [r3]
#endif
#endif
}
 7a4:	e8bd8010 	ldmia	sp!, {r4, pc}
 7a8:	e002c000 	and	ip, r2, r0
 7ac:	e000c000 	and	ip, r0, r0
 7b0:	fffff000 	undefined instruction 0xfffff000
 7b4:	4000008e 	andmi	r0, r0, lr, lsl #1
 7b8:	40000198 	mulmi	r0, r8, r1
 7bc:	0000013c 	andeq	r0, r0, ip, lsr r1
 7c0:	40000226 	andmi	r0, r0, r6, lsr #4
 7c4:	400001a0 	andmi	r0, r0, r0, lsr #3
 7c8:	40000190 	mulmi	r0, r0, r1

000007cc <uart0Putch>:

/******************************************************************************
 *
 * Function Name: uart0Putch()
 *
 * Description:  
 *    This function puts a character into the UART output queue for
 *    transmission.
 *
 * Calling Sequence: 
 *    character to be transmitted
 *
 * Returns:
 *    ch on success, -1 on error (queue full)
 *
 *****************************************************************************/
int uart0Putch(int ch)
{
 7cc:	e92d40f0 	stmdb	sp!, {r4, r5, r6, r7, lr}
#ifdef UART0_TX_INT_MODE
  uint16_t temp;
  unsigned cpsr;

  temp = (uart0_tx_insert_idx + 1) % UART0_TX_BUFFER_SIZE;
 7d0:	e59f6094 	ldr	r6, [pc, #148]	; 86c <.text+0x86c>
 7d4:	e1d630b0 	ldrh	r3, [r6]
 7d8:	e59f2090 	ldr	r2, [pc, #144]	; 870 <.text+0x870>
 7dc:	e2833001 	add	r3, r3, #1	; 0x1
 7e0:	e0032002 	and	r2, r3, r2

  if (temp == uart0_tx_extract_idx)
 7e4:	e59f3088 	ldr	r3, [pc, #136]	; 874 <.text+0x874>
 7e8:	e1a02802 	mov	r2, r2, lsl #16
 7ec:	e1d330b0 	ldrh	r3, [r3]
 7f0:	e1a05822 	mov	r5, r2, lsr #16
 7f4:	e1530005 	cmp	r3, r5
    return -1;                          // no room

  cpsr = disableIRQ();                  // disable global interrupts
  U0IER &= ~UIER_ETBEI;                 // disable TX interrupts
 7f8:	e59f7078 	ldr	r7, [pc, #120]	; 878 <.text+0x878>
 7fc:	e3e03000 	mvn	r3, #0	; 0x0
 800:	e1a04000 	mov	r4, r0
 804:	0a000016 	beq	864 <uart0Putch+0x98>
 808:	ebffff15 	bl	464 <disableIRQ>
 80c:	e5d73004 	ldrb	r3, [r7, #4]
 810:	e20330fd 	and	r3, r3, #253	; 0xfd
 814:	e5c73004 	strb	r3, [r7, #4]
  restoreIRQ(cpsr);                     // restore global interrupts
 818:	ebffff15 	bl	474 <restoreIRQ>

  // check if in process of sending data
  if (uart0_tx_running)
 81c:	e59f1058 	ldr	r1, [pc, #88]	; 87c <.text+0x87c>
 820:	e5913000 	ldr	r3, [r1]
 824:	e3530000 	cmp	r3, #0	; 0x0
    {
    // add to queue
    uart0_tx_buffer[uart0_tx_insert_idx] = (uint8_t)ch;
    uart0_tx_insert_idx = temp;
    }
  else
    {
    // set running flag and write to output register
    uart0_tx_running = 1;
    U0THR = (uint8_t)ch;
 828:	e20420ff 	and	r2, r4, #255	; 0xff
 82c:	159f304c 	ldrne	r3, [pc, #76]	; 880 <.text+0x880>
 830:	11d620b0 	ldrneh	r2, [r6]
 834:	03a03001 	moveq	r3, #1	; 0x1
 838:	17c24003 	strneb	r4, [r2, r3]
 83c:	05813000 	streq	r3, [r1]
 840:	05c72000 	streqb	r2, [r7]
 844:	11c650b0 	strneh	r5, [r6]
    }

  cpsr = disableIRQ();                  // disable global interrupts
 848:	ebffff05 	bl	464 <disableIRQ>
  U0IER |= UIER_ETBEI;                  // enable TX interrupts
 84c:	e59f2024 	ldr	r2, [pc, #36]	; 878 <.text+0x878>
 850:	e5d23004 	ldrb	r3, [r2, #4]
 854:	e3833002 	orr	r3, r3, #2	; 0x2
 858:	e5c23004 	strb	r3, [r2, #4]
  restoreIRQ(cpsr);                     // restore global interrupts
 85c:	ebffff04 	bl	474 <restoreIRQ>
#else
  while (!(U0LSR & ULSR_THRE))          // wait for TX buffer to empty
    continue;                           // also either WDOG() or swap()

  U0THR = (uint8_t)ch;