main.lss

rtc code for lpc2148

 1e4:	e59f30c8 	ldr	r3, [pc, #200]	; 2b4 <.text+0x2b4>
 1e8:	b1e01ca1 	mvnlt	r1, r1, lsr #25
 1ec:	e7cc2003 	strb	r2, [ip, r3]
 1f0:	b2811001 	addlt	r1, r1, #1	; 0x1
 1f4:	e1a03801 	mov	r3, r1, lsl #16
 1f8:	e1a03823 	mov	r3, r3, lsr #16
 1fc:	e5de2014 	ldrb	r2, [lr, #20]
 200:	e1530006 	cmp	r3, r6
 204:	11a0c003 	movne	ip, r3
 208:	e3120001 	tst	r2, #1	; 0x1
 20c:	0a000011 	beq	258 <.text+0x258>
 210:	eaffffeb 	b	1c4 <.text+0x1c4>
 214:	e1550000 	cmp	r5, r0
 218:	0a000009 	beq	244 <.text+0x244>
            {
            U0THR = uart0_tx_buffer[uart0_tx_extract_idx++];
 21c:	e59f3094 	ldr	r3, [pc, #148]	; 2b8 <.text+0x2b8>
 220:	e7d03003 	ldrb	r3, [r0, r3]
 224:	e5c13000 	strb	r3, [r1]
            uart0_tx_extract_idx %= UART0_TX_BUFFER_SIZE;
 228:	e202007f 	and	r0, r2, #127	; 0x7f
 22c:	e59f1078 	ldr	r1, [pc, #120]	; 2ac <.text+0x2ac>
 230:	e5d13014 	ldrb	r3, [r1, #20]
 234:	e3130020 	tst	r3, #32	; 0x20
 238:	e2802001 	add	r2, r0, #1	; 0x1
 23c:	1afffff4 	bne	214 <.text+0x214>
 240:	ea000004 	b	258 <.text+0x258>
 244:	e3a04000 	mov	r4, #0	; 0x0
 248:	ea000002 	b	258 <.text+0x258>
            }
          else
            {
            // no
            uart0_tx_running = 0;       // clear running flag
            break;
            }
          }

        break;
#endif // UART0_TX_INT_MODE

      default:                          // Unknown
        U0LSR;
 24c:	e59f3058 	ldr	r3, [pc, #88]	; 2ac <.text+0x2ac>
 250:	e5d32014 	ldrb	r2, [r3, #20]
        U0RBR;
 254:	e5d33000 	ldrb	r3, [r3]
 258:	e59f304c 	ldr	r3, [pc, #76]	; 2ac <.text+0x2ac>
 25c:	e5d32008 	ldrb	r2, [r3, #8]
 260:	e2223001 	eor	r3, r2, #1	; 0x1
 264:	e2131001 	ands	r1, r3, #1	; 0x1
 268:	1affffc2 	bne	178 <uart0ISR+0x3c>
 26c:	e59f302c 	ldr	r3, [pc, #44]	; 2a0 <.text+0x2a0>
 270:	e5834000 	str	r4, [r3]
 274:	e59f3028 	ldr	r3, [pc, #40]	; 2a4 <.text+0x2a4>
 278:	e1c300b0 	strh	r0, [r3]
 27c:	e59f3024 	ldr	r3, [pc, #36]	; 2a8 <.text+0x2a8>
 280:	e1c3c0b0 	strh	ip, [r3]
        break;
      }
    }

  VICVectAddr = 0x00000000;             // clear this interrupt from the VIC
 284:	e59f3030 	ldr	r3, [pc, #48]	; 2bc <.text+0x2bc>
 288:	e5831030 	str	r1, [r3, #48]
  ISR_EXIT();                           // recover registers and return
 28c:	e8bd0002 	ldmia	sp!, {r1}
 290:	e161f001 	msr	SPSR_c, r1
 294:	e8fd9fff 	ldmia	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}^
 298:	40000226 	andmi	r0, r0, r6, lsr #4
 29c:	4000008e 	andmi	r0, r0, lr, lsl #1
 2a0:	400001a0 	andmi	r0, r0, r0, lsr #3
 2a4:	40000198 	mulmi	r0, r8, r1
 2a8:	40000190 	mulmi	r0, r0, r1
 2ac:	e000c000 	and	ip, r0, r0
 2b0:	8000007f 	andhi	r0, r0, pc, ror r0
 2b4:	400001a4 	andmi	r0, r0, r4, lsr #3
 2b8:	4000000c 	andmi	r0, r0, ip
 2bc:	fffff000 	undefined instruction 0xfffff000

000002c0 <uart1ISR>:
}
#endif // defined(UART0_TX_INT_MODE) || defined(UART0_RX_INT_MODE)
#endif // UART0_SUPPORT


#if UART1_SUPPORT

#ifdef UART1_RX_INT_MODE
extern uint8_t  uart1_rx_buffer[UART1_RX_BUFFER_SIZE];
extern uint16_t uart1_rx_insert_idx, uart1_rx_extract_idx;
#endif // UART1_RX_INT_MODE

#ifdef UART1_TX_INT_MODE
extern uint8_t  uart1_tx_buffer[UART1_TX_BUFFER_SIZE];
extern uint16_t uart1_tx_insert_idx, uart1_tx_extract_idx;
extern int      uart1_tx_running;
#endif // UART1_TX_INT_MODE

#if defined(UART1_TX_INT_MODE) || defined(UART1_RX_INT_MODE)
/******************************************************************************
 *
 * Function Name: uart1ISR()
 *
 * Description:
 *    This function implements the ISR for UART1.
 *
 * Calling Sequence: 
 *    void
 *
 * Returns:
 *    void
 *
 *****************************************************************************/
void uart1ISR(void)
{
  uint8_t iid;

  // perform proper ISR entry so thumb-interwork works properly
  ISR_ENTRY();
 2c0:	e24ee004 	sub	lr, lr, #4	; 0x4
 2c4:	e92d5fff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
 2c8:	e14f1000 	mrs	r1, SPSR
 2cc:	e92d0002 	stmdb	sp!, {r1}

  // loop until not more interrupt sources
  while (((iid = U1IIR) & UIIR_NO_INT) == 0)
    {
    // identify & process the highest priority interrupt
    switch (iid & UIIR_ID_MASK)
      {
      case UIIR_RLS_INT:                // Receive Line Status
        U1LSR;                          // read LSR to clear
        break;

#ifdef UART1_RX_INT_MODE
      case UIIR_CTI_INT:                // Character Timeout Indicator
      case UIIR_RDA_INT:                // Receive Data Available
        do
          {
          uint16_t temp;

          // calc next insert index & store character
          temp = (uart1_rx_insert_idx + 1) % UART1_RX_BUFFER_SIZE;
          uart1_rx_buffer[uart1_rx_insert_idx] = U1RBR;

          // check for more room in queue
          if (temp != uart1_rx_extract_idx)
 2d0:	e59f3154 	ldr	r3, [pc, #340]	; 42c <.text+0x42c>
 2d4:	e1d360b0 	ldrh	r6, [r3]
            uart1_rx_insert_idx = temp; // update insert index
          }
        while (U1LSR & ULSR_RDR);

        break;
#endif

#ifdef UART1_TX_INT_MODE
      case UIIR_THRE_INT:               // Transmit Holding Register Empty
        while (U1LSR & ULSR_THRE)
          {
          // check if more data to send
          if (uart1_tx_insert_idx != uart1_tx_extract_idx)
 2d8:	e59f3150 	ldr	r3, [pc, #336]	; 430 <.text+0x430>
 2dc:	e1d350b0 	ldrh	r5, [r3]
 2e0:	e59f314c 	ldr	r3, [pc, #332]	; 434 <.text+0x434>
 2e4:	e5934000 	ldr	r4, [r3]
 2e8:	e59f3148 	ldr	r3, [pc, #328]	; 438 <.text+0x438>
 2ec:	e1d300b0 	ldrh	r0, [r3]
 2f0:	e59f3144 	ldr	r3, [pc, #324]	; 43c <.text+0x43c>
 2f4:	e1d3c0b0 	ldrh	ip, [r3]
 2f8:	ea00003b 	b	3ec <.text+0x3ec>
 2fc:	e202300e 	and	r3, r2, #14	; 0xe
 300:	e353000c 	cmp	r3, #12	; 0xc
 304:	979ff103 	ldrls	pc, [pc, r3, lsl #2]
 308:	ea000033 	b	3dc <.text+0x3dc>
 30c:	000003cc 	andeq	r0, r0, ip, asr #7
 310:	000003dc 	ldreqd	r0, [r0], -ip
 314:	000003b4 	streqh	r0, [r0], -r4
 318:	000003dc 	ldreqd	r0, [r0], -ip
 31c:	0000034c 	andeq	r0, r0, ip, asr #6
 320:	000003dc 	ldreqd	r0, [r0], -ip
 324:	00000340 	andeq	r0, r0, r0, asr #6
 328:	000003dc 	ldreqd	r0, [r0], -ip
 32c:	000003dc 	ldreqd	r0, [r0], -ip
 330:	000003dc 	ldreqd	r0, [r0], -ip
 334:	000003dc 	ldreqd	r0, [r0], -ip
 338:	000003dc 	ldreqd	r0, [r0], -ip
 33c:	0000034c 	andeq	r0, r0, ip, asr #6
 340:	e59f30f8 	ldr	r3, [pc, #248]	; 440 <.text+0x440>
 344:	e5d33014 	ldrb	r3, [r3, #20]
 348:	ea000027 	b	3ec <.text+0x3ec>
 34c:	e59f10f0 	ldr	r1, [pc, #240]	; 444 <.text+0x444>
 350:	e28c3001 	add	r3, ip, #1	; 0x1
 354:	e0031001 	and	r1, r3, r1
 358:	e3510000 	cmp	r1, #0	; 0x0
 35c:	e59fe0dc 	ldr	lr, [pc, #220]	; 440 <.text+0x440>
 360:	b2411001 	sublt	r1, r1, #1	; 0x1
 364:	b1e01c81 	mvnlt	r1, r1, lsl #25
 368:	e5de2000 	ldrb	r2, [lr]
 36c:	e59f30d4 	ldr	r3, [pc, #212]	; 448 <.text+0x448>
 370:	b1e01ca1 	mvnlt	r1, r1, lsr #25
 374:	e7cc2003 	strb	r2, [ip, r3]
 378:	b2811001 	addlt	r1, r1, #1	; 0x1
 37c:	e1a03801 	mov	r3, r1, lsl #16
 380:	e1a03823 	mov	r3, r3, lsr #16
 384:	e5de2014 	ldrb	r2, [lr, #20]
 388:	e1530006 	cmp	r3, r6
 38c:	11a0c003 	movne	ip, r3
 390:	e3120001 	tst	r2, #1	; 0x1
 394:	0a000014 	beq	3ec <.text+0x3ec>
 398:	eaffffeb 	b	34c <.text+0x34c>
 39c:	e1550000 	cmp	r5, r0
 3a0:	0a00000b 	beq	3d4 <.text+0x3d4>
            {
            U1THR = uart1_tx_buffer[uart1_tx_extract_idx++];
 3a4:	e59f30a0 	ldr	r3, [pc, #160]	; 44c <.text+0x44c>
 3a8:	e7d03003 	ldrb	r3, [r0, r3]
 3ac:	e5c13000 	strb	r3, [r1]
            uart1_tx_extract_idx %= UART1_TX_BUFFER_SIZE;
 3b0:	e202007f 	and	r0, r2, #127	; 0x7f
 3b4:	e59f1084 	ldr	r1, [pc, #132]	; 440 <.text+0x440>
 3b8:	e5d13014 	ldrb	r3, [r1, #20]
 3bc:	e3130020 	tst	r3, #32	; 0x20
 3c0:	e2802001 	add	r2, r0, #1	; 0x1
 3c4:	1afffff4 	bne	39c <.text+0x39c>
 3c8:	ea000007 	b	3ec <.text+0x3ec>
            }
          else
            {
            // no
            uart1_tx_running = 0;       // clear running flag
            break;
            }
          }

        break;
#endif // UART1_TX_INT_MODE

      case UIIR_MS_INT:                 // MODEM Status
        U1MSR;                          // read MSR to clear
 3cc:	e59f306c 	ldr	r3, [pc, #108]	; 440 <.text+0x440>
 3d0:	ea000004 	b	3e8 <.text+0x3e8>
 3d4:	e3a04000 	mov	r4, #0	; 0x0
 3d8:	ea000003 	b	3ec <.text+0x3ec>
        break;

      default:                          // Unknown
        U1LSR;
 3dc:	e59f305c 	ldr	r3, [pc, #92]	; 440 <.text+0x440>
 3e0:	e5d32014 	ldrb	r2, [r3, #20]
        U1RBR;
 3e4:	e5d32000 	ldrb	r2, [r3]
        U1MSR;
 3e8:	e5d33018 	ldrb	r3, [r3, #24]
 3ec:	e59f304c 	ldr	r3, [pc, #76]	; 440 <.text+0x440>
 3f0:	e5d32008 	ldrb	r2, [r3, #8]
 3f4:	e2223001 	eor	r3, r2, #1	; 0x1
 3f8:	e2131001 	ands	r1, r3, #1	; 0x1
 3fc:	1affffbe 	bne	2fc <uart1ISR+0x3c>
 400:	e59f302c 	ldr	r3, [pc, #44]	; 434 <.text+0x434>
 404:	e5834000 	str	r4, [r3]
 408:	e59f3028 	ldr	r3, [pc, #40]	; 438 <.text+0x438>
 40c:	e1c300b0 	strh	r0, [r3]
 410:	e59f3024 	ldr	r3, [pc, #36]	; 43c <.text+0x43c>
 414:	e1c3c0b0 	strh	ip, [r3]
        break;
      }
    }

  VICVectAddr = 0x00000000;             // clear this interrupt from the VIC
 418:	e59f3030 	ldr	r3, [pc, #48]	; 450 <.text+0x450>
 41c:	e5831030 	str	r1, [r3, #48]
  ISR_EXIT();                           // recover registers and return
 420:	e8bd0002 	ldmia	sp!, {r1}
 424:	e161f001 	msr	SPSR_c, r1
 428:	e8fd9fff 	ldmia	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}^
 42c:	4000019c 	mulmi	r0, ip, r1
 430:	4000019a 	mulmi	r0, sl, r1
 434:	40000194 	mulmi	r0, r4, r1
 438:	40000224 	andmi	r0, r0, r4, lsr #4
 43c:	4000008c 	andmi	r0, r0, ip, lsl #1
 440:	e0010000 	and	r0, r1, r0
 444:	8000007f 	andhi	r0, r0, pc, ror r0
 448:	40000110 	andmi	r0, r0, r0, lsl r1
 44c:	40000090 	mulmi	r0, r0, r0
 450:	fffff000 	undefined instruction 0xfffff000

00000454 <enableFIQ>:

static inline unsigned __get_cpsr(void)
{
  unsigned long retval;
  asm volatile (" mrs  %0, cpsr" : "=r" (retval) : /* no inputs */  );
 454:	e10f0000 	mrs	r0, CPSR
  return retval;
}

static inline void __set_cpsr(unsigned val)
{
  asm volatile (" msr  cpsr, %0" : /* no outputs */ : "r" (val)  );
 458:	e3c03040 	bic	r3, r0, #64	; 0x40
 45c:	e129f003 	msr	CPSR_fc, r3
}

unsigned disableIRQ(void)
{
  unsigned _cpsr;

  _cpsr = __get_cpsr();
  __set_cpsr(_cpsr | IRQ_MASK);
  return _cpsr;
}

unsigned restoreIRQ(unsigned oldCPSR)
{
  unsigned _cpsr;

  _cpsr = __get_cpsr();
  __set_cpsr((_cpsr & ~IRQ_MASK) | (oldCPSR & IRQ_MASK));
  return _cpsr;
}

unsigned enableIRQ(void)
{
  unsigned _cpsr;

  _cpsr = __get_cpsr();
  __set_cpsr(_cpsr & ~IRQ_MASK);
  return _cpsr;
}

unsigned disableFIQ(void)
{
  unsigned _cpsr;

  _cpsr = __get_cpsr();
  __set_cpsr(_cpsr | FIQ_MASK);
  return _cpsr;
}

unsigned restoreFIQ(unsigned oldCPSR)
{
  unsigned _cpsr;

  _cpsr = __get_cpsr();
  __set_cpsr((_cpsr & ~FIQ_MASK) | (oldCPSR & FIQ_MASK));
  return _cpsr;
}

unsigned enableFIQ(void)
{
  unsigned _cpsr;

  _cpsr = __get_cpsr();
  __set_cpsr(_cpsr & ~FIQ_MASK);
  return _cpsr;
}
 460:	e12fff1e 	bx	lr

00000464 <disableIRQ>:
 464:	e10f0000 	mrs	r0, CPSR
 468:	e3803080 	orr	r3, r0, #128	; 0x80
 46c:	e129f003 	msr	CPSR_fc, r3
 470:	e12fff1e 	bx	lr

00000474 <restoreIRQ>:
 474:	e10f2000 	mrs	r2, CPSR
 478:	e2000080 	and	r0, r0, #128	; 0x80
 47c:	e3c23080 	bic	r3, r2, #128	; 0x80
 480:	e1833000 	orr	r3, r3, r0
 484:	e129f003 	msr	CPSR_fc, r3
 488:	e1a00002 	mov	r0, r2
 48c:	e12fff1e 	bx	lr

00000490 <enableIRQ>:
 490:	e10f0000 	mrs	r0, CPSR
 494:	e3c03080 	bic	r3, r0, #128	; 0x80
 498:	e129f003 	msr	CPSR_fc, r3
 49c:	e12fff1e 	bx	lr

000004a0 <disableFIQ>:
 4a0:	e10f0000 	mrs	r0, CPSR
 4a4:	e3803040 	orr	r3, r0, #64	; 0x40
 4a8:	e129f003 	msr	CPSR_fc, r3
 4ac:	e12fff1e 	bx	lr

000004b0 <restoreFIQ>:
 4b0:	e10f2000 	mrs	r2, CPSR
 4b4:	e2000040 	and	r0, r0, #64	; 0x40
 4b8:	e3c23040 	bic	r3, r2, #64	; 0x40
 4bc:	e1833000 	orr	r3, r3, r0
 4c0:	e129f003 	msr	CPSR_fc, r3
 4c4:	e1a00002 	mov	r0, r2
 4c8:	e12fff1e 	bx	lr

000004cc <rtc0>:

}
/*************************************************************/
void rtc0(void)