📄 main.lss
字号:
main.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00000e4c 00000000 00000000 00008000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .bss 00000228 40000000 40000000 00008e4c 2**2
ALLOC
2 .stack 00000400 40000300 40000300 00008e4c 2**0
ALLOC
3 .comment 00000087 00000000 00000000 00008e4c 2**0
CONTENTS, READONLY
4 .debug_aranges 000000c0 00000000 00000000 00008ed8 2**3
CONTENTS, READONLY, DEBUGGING
5 .debug_pubnames 00000370 00000000 00000000 00008f98 2**0
CONTENTS, READONLY, DEBUGGING
6 .debug_info 00000c6f 00000000 00000000 00009308 2**0
CONTENTS, READONLY, DEBUGGING
7 .debug_abbrev 000004d3 00000000 00000000 00009f77 2**0
CONTENTS, READONLY, DEBUGGING
8 .debug_line 000003fe 00000000 00000000 0000a44a 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_frame 000002f8 00000000 00000000 0000a848 2**2
CONTENTS, READONLY, DEBUGGING
10 .debug_str 000003ab 00000000 00000000 0000ab40 2**0
CONTENTS, READONLY, DEBUGGING
11 .debug_loc 00000350 00000000 00000000 0000aeeb 2**0
CONTENTS, READONLY, DEBUGGING
12 .debug_ranges 00000058 00000000 00000000 0000b23b 2**0
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
00000000 <_boot>:
// Runtime Interrupt Vectors
// -------------------------
Vectors:
b _start // reset - _start
0: ea000012 b 50 <_mainCRTStartup>
ldr pc,_undf // undefined - _undf
4: e59ff014 ldr pc, [pc, #20] ; 20 <_undf>
ldr pc,_swi // SWI - _swi
8: e59ff014 ldr pc, [pc, #20] ; 24 <_swi>
ldr pc,_pabt // program abort - _pabt
c: e59ff014 ldr pc, [pc, #20] ; 28 <_pabt>
ldr pc,_dabt // data abort - _dabt
10: e59ff014 ldr pc, [pc, #20] ; 2c <_dabt>
nop // reserved
14: e1a00000 nop (mov r0,r0)
ldr pc,[pc,#-0xFF0] // IRQ - read the VIC
18: e51ffff0 ldr pc, [pc, #-4080] ; fffff030 <_stack+0xbfffe930>
ldr pc,_fiq // FIQ - _fiq
1c: e59ff010 ldr pc, [pc, #16] ; 34 <_fiq>
00000020 <_undf>:
20: 00000038 andeq r0, r0, r8, lsr r0
00000024 <_swi>:
24: 0000003c andeq r0, r0, ip, lsr r0
00000028 <_pabt>:
28: 00000040 andeq r0, r0, r0, asr #32
0000002c <_dabt>:
2c: 00000044 andeq r0, r0, r4, asr #32
00000030 <_irq>:
30: 00000048 andeq r0, r0, r8, asr #32
00000034 <_fiq>:
34: 0000004c andeq r0, r0, ip, asr #32
00000038 <__undf>:
#if 0
// Use this group for production
_undf: .word _reset // undefined - _reset
_swi: .word _reset // SWI - _reset
_pabt: .word _reset // program abort - _reset
_dabt: .word _reset // data abort - _reset
_irq: .word _reset // IRQ - _reset
_fiq: .word _reset // FIQ - _reset
#else
// Use this group for development
_undf: .word __undf // undefined
_swi: .word __swi // SWI
_pabt: .word __pabt // program abort
_dabt: .word __dabt // data abort
_irq: .word __irq // IRQ
_fiq: .word __fiq // FIQ
__undf: b . // undefined
38: eafffffe b 38 <__undf>
0000003c <__swi>:
__swi: b . // SWI
3c: eafffffe b 3c <__swi>
00000040 <__pabt>:
__pabt: b . // program abort
40: eafffffe b 40 <__pabt>
00000044 <__dabt>:
__dabt: b . // data abort
44: eafffffe b 44 <__dabt>
00000048 <__irq>:
__irq: b . // IRQ
48: eafffffe b 48 <__irq>
0000004c <__fiq>:
__fiq: b . // FIQ
4c: eafffffe b 4c <__fiq>
00000050 <_mainCRTStartup>:
#endif
.size _boot, . - _boot
.endfunc
// Setup the operating mode & stack.
// ---------------------------------
.global _start, start, _mainCRTStartup
.func _start
_start:
start:
_mainCRTStartup:
// Initialize Interrupt System
// - Set stack location for each mode
// - Leave in System Mode with Interrupts Disabled
// -----------------------------------------------
ldr r0,=_stack
50: e59f00c0 ldr r0, [pc, #192] ; 118 <.text+0x118>
msr CPSR_c,#MODE_UND|I_BIT|F_BIT // Undefined Instruction Mode
54: e321f0db msr CPSR_c, #219 ; 0xdb
mov sp,r0
58: e1a0d000 mov sp, r0
sub r0,r0,#UND_STACK_SIZE
5c: e2400004 sub r0, r0, #4 ; 0x4
msr CPSR_c,#MODE_ABT|I_BIT|F_BIT // Abort Mode
60: e321f0d7 msr CPSR_c, #215 ; 0xd7
mov sp,r0
64: e1a0d000 mov sp, r0
sub r0,r0,#ABT_STACK_SIZE
68: e2400004 sub r0, r0, #4 ; 0x4
msr CPSR_c,#MODE_FIQ|I_BIT|F_BIT // FIQ Mode
6c: e321f0d1 msr CPSR_c, #209 ; 0xd1
mov sp,r0
70: e1a0d000 mov sp, r0
sub r0,r0,#FIQ_STACK_SIZE
74: e2400004 sub r0, r0, #4 ; 0x4
msr CPSR_c,#MODE_IRQ|I_BIT|F_BIT // IRQ Mode
78: e321f0d2 msr CPSR_c, #210 ; 0xd2
mov sp,r0
7c: e1a0d000 mov sp, r0
sub r0,r0,#IRQ_STACK_SIZE
80: e2400080 sub r0, r0, #128 ; 0x80
msr CPSR_c,#MODE_SVC|I_BIT|F_BIT // Supervisor Mode
84: e321f0d3 msr CPSR_c, #211 ; 0xd3
mov sp,r0
88: e1a0d000 mov sp, r0
sub r0,r0,#SVC_STACK_SIZE
8c: e2400004 sub r0, r0, #4 ; 0x4
msr CPSR_c,#MODE_SYS|I_BIT|F_BIT // System Mode
90: e321f0df msr CPSR_c, #223 ; 0xdf
mov sp,r0
94: e1a0d000 mov sp, r0
// Copy initialized data to its execution address in RAM
// -----------------------------------------------------
#ifdef ROM_RUN
ldr r1,=_etext // -> ROM data start
98: e59f107c ldr r1, [pc, #124] ; 11c <.text+0x11c>
ldr r2,=_data // -> data start
9c: e59f207c ldr r2, [pc, #124] ; 120 <.text+0x120>
ldr r3,=_edata // -> end of data
a0: e59f307c ldr r3, [pc, #124] ; 124 <.text+0x124>
1: cmp r2,r3 // check if data to move
a4: e1520003 cmp r2, r3
ldrlo r0,[r1],#4 // copy it
a8: 34910004 ldrcc r0, [r1], #4
strlo r0,[r2],#4
ac: 34820004 strcc r0, [r2], #4
blo 1b // loop until done
b0: 3afffffb bcc a4 <IRQ_STACK_SIZE+0x24>
#endif
// Clear .bss
// ----------
mov r0,#0 // get a zero
b4: e3a00000 mov r0, #0 ; 0x0
ldr r1,=__bss_start // -> bss start
b8: e59f1068 ldr r1, [pc, #104] ; 128 <.text+0x128>
ldr r2,=__bss_end__ // -> bss end
bc: e59f2068 ldr r2, [pc, #104] ; 12c <.text+0x12c>
2: cmp r1,r2 // check if data to clear
c0: e1510002 cmp r1, r2
strlo r0,[r1],#4 // clear 4 bytes
c4: 34810004 strcc r0, [r1], #4
blo 2b // loop until done
c8: 3afffffc bcc c0 <IRQ_STACK_SIZE+0x40>
/*
Call C++ constructors (for objects in "global scope")
ctor loop added by Martin Thomas 4/2005
based on a Anglia Design example-application for ST ARM
*/
LDR r0, =__ctors_start__
cc: e59f005c ldr r0, [pc, #92] ; 130 <.text+0x130>
LDR r1, =__ctors_end__
d0: e59f105c ldr r1, [pc, #92] ; 134 <.text+0x134>
000000d4 <ctor_loop>:
ctor_loop:
CMP r0, r1
d4: e1500001 cmp r0, r1
BEQ ctor_end
d8: 0a000005 beq f4 <ctor_end>
LDR r2, [r0], #4
dc: e4902004 ldr r2, [r0], #4
STMFD sp!, {r0-r1}
e0: e92d0003 stmdb sp!, {r0, r1}
MOV lr, pc
e4: e1a0e00f mov lr, pc
MOV pc, r2
e8: e1a0f002 mov pc, r2
LDMFD sp!, {r0-r1}
ec: e8bd0003 ldmia sp!, {r0, r1}
B ctor_loop
f0: eafffff7 b d4 <ctor_loop>
000000f4 <ctor_end>:
ctor_end:
// Call main program: main(0)
// --------------------------
mov r0,#0 // no arguments (argc = 0)
f4: e3a00000 mov r0, #0 ; 0x0
mov r1,r0
f8: e1a01000 mov r1, r0
mov r2,r0
fc: e1a02000 mov r2, r0
mov fp,r0 // null frame pointer
100: e1a0b000 mov fp, r0
mov r7,r0 // null frame pointer for thumb
104: e1a07000 mov r7, r0
ldr r10,=main
108: e59fa028 ldr sl, [pc, #40] ; 138 <.text+0x138>
mov lr,pc
10c: e1a0e00f mov lr, pc
/* Enter the C code, use BX instruction so as to never return */
/* use BLX (?) main if you want to use c++ destructors below */
bx r10 // enter main()
110: e12fff1a bx sl
00000114 <_reset>:
/* "global object"-dtors are never called and it should not be
needed since there is no OS to exit to. */
/* Call destructors */
# LDR r0, =__dtors_start__
# LDR r1, =__dtors_end__
dtor_loop:
# CMP r0, r1
# BEQ dtor_end
# LDR r2, [r0], #4
# STMFD sp!, {r0-r1}
# MOV lr, pc
# MOV pc, r2
# LDMFD sp!, {r0-r1}
# B dtor_loop
dtor_end:
.size _start, . - _start
.endfunc
.global _reset, reset, exit, abort
.func _reset
_reset:
reset:
exit:
abort:
#if 0
// Disable interrupts, then force a hardware reset by driving P23 low
// -------------------------------------------------------------------
mrs r0,cpsr // get PSR
orr r0,r0,#I_BIT|F_BIT // disable IRQ and FIQ
msr cpsr,r0 // set up status register
ldr r1,=(PS_BASE) // PS Base Address
ldr r0,=(PS_PIO) // PIO Module
str r0,[r1,#PS_PCER_OFF] // enable its clock
ldr r1,=(PIO_BASE) // PIO Base Address
ldr r0,=(1<<23) // P23
str r0,[r1,#PIO_PER_OFF] // make sure pin is contolled by PIO
str r0,[r1,#PIO_CODR_OFF] // set the pin low
str r0,[r1,#PIO_OER_OFF] // make it an output
#endif
b . // loop until reset
114: eafffffe b 114 <_reset>
118: 40000700 andmi r0, r0, r0, lsl #14
11c: 00000e4c andeq r0, r0, ip, asr #28
120: 40000000 andmi r0, r0, r0
124: 00000e4c andeq r0, r0, ip, asr #28
128: 40000000 andmi r0, r0, r0
12c: 40000228 andmi r0, r0, r8, lsr #4
130: 00000e4c andeq r0, r0, ip, asr #28
134: 00000e4c andeq r0, r0, ip, asr #28
138: 000005f8 streqd r0, [r0], -r8
0000013c <uart0ISR>:
{
uint8_t iid;
// perform proper ISR entry so thumb-interwork works properly
ISR_ENTRY();
13c: e24ee004 sub lr, lr, #4 ; 0x4
140: e92d5fff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
144: e14f1000 mrs r1, SPSR
148: e92d0002 stmdb sp!, {r1}
// loop until not more interrupt sources
while (((iid = U0IIR) & UIIR_NO_INT) == 0)
{
// identify & process the highest priority interrupt
switch (iid & UIIR_ID_MASK)
{
case UIIR_RLS_INT: // Receive Line Status
U0LSR; // read LSR to clear
break;
#ifdef UART0_RX_INT_MODE
case UIIR_CTI_INT: // Character Timeout Indicator
case UIIR_RDA_INT: // Receive Data Available
do
{
uint16_t temp;
// calc next insert index & store character
temp = (uart0_rx_insert_idx + 1) % UART0_RX_BUFFER_SIZE;
uart0_rx_buffer[uart0_rx_insert_idx] = U0RBR;
// check for more room in queue
if (temp != uart0_rx_extract_idx)
14c: e59f3144 ldr r3, [pc, #324] ; 298 <.text+0x298>
150: e1d360b0 ldrh r6, [r3]
uart0_rx_insert_idx = temp; // update insert index
}
while (U0LSR & ULSR_RDR);
break;
#endif
#ifdef UART0_TX_INT_MODE
case UIIR_THRE_INT: // Transmit Holding Register Empty
while (U0LSR & ULSR_THRE)
{
// check if more data to send
if (uart0_tx_insert_idx != uart0_tx_extract_idx)
154: e59f3140 ldr r3, [pc, #320] ; 29c <.text+0x29c>
158: e1d350b0 ldrh r5, [r3]
15c: e59f313c ldr r3, [pc, #316] ; 2a0 <.text+0x2a0>
160: e5934000 ldr r4, [r3]
164: e59f3138 ldr r3, [pc, #312] ; 2a4 <.text+0x2a4>
168: e1d300b0 ldrh r0, [r3]
16c: e59f3134 ldr r3, [pc, #308] ; 2a8 <.text+0x2a8>
170: e1d3c0b0 ldrh ip, [r3]
174: ea000037 b 258 <.text+0x258>
178: e202300e and r3, r2, #14 ; 0xe
17c: e2433002 sub r3, r3, #2 ; 0x2
180: e353000a cmp r3, #10 ; 0xa
184: 979ff103 ldrls pc, [pc, r3, lsl #2]
188: ea00002f b 24c <.text+0x24c>
18c: 0000022c andeq r0, r0, ip, lsr #4
190: 0000024c andeq r0, r0, ip, asr #4
194: 000001c4 andeq r0, r0, r4, asr #3
198: 0000024c andeq r0, r0, ip, asr #4
19c: 000001b8 streqh r0, [r0], -r8
1a0: 0000024c andeq r0, r0, ip, asr #4
1a4: 0000024c andeq r0, r0, ip, asr #4
1a8: 0000024c andeq r0, r0, ip, asr #4
1ac: 0000024c andeq r0, r0, ip, asr #4
1b0: 0000024c andeq r0, r0, ip, asr #4
1b4: 000001c4 andeq r0, r0, r4, asr #3
1b8: e59f30ec ldr r3, [pc, #236] ; 2ac <.text+0x2ac>
1bc: e5d33014 ldrb r3, [r3, #20]
1c0: ea000024 b 258 <.text+0x258>
1c4: e59f10e4 ldr r1, [pc, #228] ; 2b0 <.text+0x2b0>
1c8: e28c3001 add r3, ip, #1 ; 0x1
1cc: e0031001 and r1, r3, r1
1d0: e3510000 cmp r1, #0 ; 0x0
1d4: e59fe0d0 ldr lr, [pc, #208] ; 2ac <.text+0x2ac>
1d8: b2411001 sublt r1, r1, #1 ; 0x1
1dc: b1e01c81 mvnlt r1, r1, lsl #25
1e0: e5de2000 ldrb r2, [lr]
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