📄 uart.lst
字号:
355 0268 600050E3 .L41:
356 026c 0000A013 .word -536821760
357 0270 0100A003 .LFE7:
359 .align 2
360 .global uart0TxFlush
362 uart0TxFlush:
363 .LFB8:
364 .loc 1 288 0
365 0278 00C000E0 @ args = 0, pretend = 0, frame = 0
366 @ frame_needed = 0, uses_anonymous_args = 0
367 .LVL29:
368 stmfd sp!, {r4, lr}
369 .LCFI4:
370 .loc 1 292 0
371 ldr r4, .L45
372 ldrb r3, [r4, #8] @ zero_extendqisi2
271:uart.c ****
272:uart.c **** /******************************************************************************
273:uart.c **** *
274:uart.c **** * Function Name: uart0TxFlush()
275:uart.c **** *
276:uart.c **** * Description:
277:uart.c **** * This function removes all characters from the UART transmit queue
278:uart.c **** * (without transmitting them).
279:uart.c **** *
280:uart.c **** * Calling Sequence:
281:uart.c **** * void
282:uart.c **** *
283:uart.c **** * Returns:
284:uart.c **** * void
285:uart.c **** *
286:uart.c **** *****************************************************************************/
287:uart.c **** void uart0TxFlush(void)
288:uart.c **** {
373 rb r3, [r4, #8]
374 .loc 1 295 0
375 bl disableIRQ
376 .loc 1 296 0
377 027c 10402DE9 ldrb r3, [r4, #4] @ zero_extendqisi2
378 and r3, r3, #253
289:uart.c **** #ifdef UART0_TX_INT_MODE
290:uart.c **** unsigned cpsr;
291:uart.c ****
292:uart.c **** U0FCR |= UFCR_TX_FIFO_RESET; // clear the TX fifo
379 r3, [r4, #4]
380 0280 34409FE5 .loc 1 297 0
381 0284 0830D4E5 bl restoreIRQ
382 0288 043083E3 .loc 1 298 0
383 028c 0830C4E5 ldr r3, .L45+4
293:uart.c ****
294:uart.c **** // "Empty" the transmit buffer.
295:uart.c **** cpsr = disableIRQ(); // disable global interrupts
384 r2, #0
385 0290 FEFFFFEB strh r2, [r3, #0] @ movhi
296:uart.c **** U0IER &= ~UIER_ETBEI; // disable TX interrupts
386 dr r3, .L45+8
387 0294 0430D4E5 strh r2, [r3, #0] @ movhi
388 0298 FD3003E2 .loc 1 302 0
389 029c 0430C4E5 ldmfd sp!, {r4, pc}
297:uart.c **** restoreIRQ(cpsr); // restore global interrupts
390 :
391 02a0 FEFFFFEB .align 2
298:uart.c **** uart0_tx_insert_idx = uart0_tx_extract_idx = 0;
392 45:
393 02a4 14309FE5 .word -536821760
394 02a8 0020A0E3 .word uart0_tx_insert_idx
395 02ac B020C3E1 .word uart0_tx_extract_idx
396 02b0 0C309FE5 .LFE8:
299:uart.c **** #else
300:uart.c **** U0FCR |= UFCR_TX_FIFO_RESET; // clear the TX fifo
301:uart.c **** #endif
302:uart.c **** }
398 n 2
399 02b8 1080BDE8 .global uart0Getch
401 uart0Getch:
402 .LFB9:
403 02bc 00C000E0 .loc 1 319 0
404 02c0 00000000 @ args = 0, pretend = 0, frame = 0
405 02c4 00000000 @ frame_needed = 0, uses_anonymous_args = 0
406 .LVL30:
407 str lr, [sp, #-4]!
408 .LCFI5:
409 .loc 1 323 0
410 ldr lr, .L52
411 ldrh r3, [lr, #0]
412 mov ip, r3, asl #16
303:uart.c ****
304:uart.c **** /******************************************************************************
305:uart.c **** *
306:uart.c **** * Function Name: uart0Getch()
307:uart.c **** *
308:uart.c **** * Description:
309:uart.c **** * This function gets a character from the UART receive queue
310:uart.c **** *
311:uart.c **** * Calling Sequence:
312:uart.c **** * void
313:uart.c **** *
314:uart.c **** * Returns:
315:uart.c **** * character on success, -1 if no character is available
316:uart.c **** *
317:uart.c **** *****************************************************************************/
318:uart.c **** int uart0Getch(void)
319:uart.c **** {
413
414 mov r2, ip, lsr #16
415 ldrh r1, [r3, #0]
416 .loc 1 326 0
417 02c8 04E02DE5 add r3, r2, #1
418 .loc 1 327 0
320:uart.c **** #ifdef UART0_RX_INT_MODE
321:uart.c **** uint8_t ch;
322:uart.c ****
323:uart.c **** if (uart0_rx_insert_idx == uart0_rx_extract_idx) // check if character is available
419 r3, r3, #127
420 02cc 34E09FE5 .loc 1 323 0
421 02d0 B030DEE1 cmp r1, r2
422 02d4 03C8A0E1 .loc 1 327 0
423 02d8 2C309FE5 strneh r3, [lr, #0] @ movhi
424 02dc 2C28A0E1 .loc 1 326 0
425 02e0 B010D3E1 ldrne r3, .L52+8
324:uart.c **** return -1;
325:uart.c ****
326:uart.c **** ch = uart0_rx_buffer[uart0_rx_extract_idx++]; // get character, bump pointer
426 r3, [r3, ip, lsr #16] @ zero_extendqisi2
427 02e4 013082E2 .LVL31:
327:uart.c **** uart0_rx_extract_idx %= UART0_RX_BUFFER_SIZE; // limit the pointer
428 loc 1 323 0
429 02e8 7F3003E2 mvn r0, #0
430 .loc 1 328 0
431 02ec 020051E1 movne r0, r3
432 .loc 1 335 0
433 02f0 B030CE11 ldr pc, [sp], #4
434 .L53:
435 02f4 14309F15 .align 2
436 02f8 2C38D317 .L52:
437 .word uart0_rx_extract_idx
438 .word uart0_rx_insert_idx
439 02fc 0000E0E3 .word uart0_rx_buffer
328:uart.c **** return ch;
440 e uart0Getch, .-uart0Getch
441 0300 0300A011 .align 2
329:uart.c **** #else
330:uart.c **** if (U0LSR & ULSR_RDR) // check if character is available
331:uart.c **** return U0RBR; // return character
332:uart.c ****
333:uart.c **** return -1;
334:uart.c **** #endif
335:uart.c **** }
442 global uart1Init
444 uart1Init:
445 .LFB10:
446 .loc 1 361 0
447 0308 00000000 @ args = 0, pretend = 0, frame = 0
448 030c 00000000 @ frame_needed = 0, uses_anonymous_args = 0
449 0310 00000000 .LVL32:
450 stmfd sp!, {r4, lr}
451 .LCFI6:
452 .loc 1 363 0
453 ldr lr, .L56
454 ldr r3, [lr, #0]
455 .loc 1 365 0
456 ldr ip, .L56+4
336:uart.c ****
337:uart.c **** #endif
338:uart.c ****
339:uart.c ****
340:uart.c **** #if UART1_SUPPORT
341:uart.c ****
342:uart.c **** /******************************************************************************
343:uart.c **** *
344:uart.c **** * Function Name: uart1Init()
345:uart.c **** *
346:uart.c **** * Description:
347:uart.c **** * This function initializes the UART for async mode
348:uart.c **** *
349:uart.c **** * Calling Sequence:
350:uart.c **** * baudrate divisor - use UART_BAUD macro
351:uart.c **** * mode - see typical modes (uart.h)
352:uart.c **** * fmode - see typical fmodes (uart.h)
353:uart.c **** *
354:uart.c **** * Returns:
355:uart.c **** * void
356:uart.c **** *
357:uart.c **** * NOTE: uart1Init(UART_BAUD(9600), UART_8N1, UART_FIFO_8);
358:uart.c **** *
359:uart.c **** *****************************************************************************/
360:uart.c **** void uart1Init(uint16_t baud, uint8_t mode, uint8_t fmode)
361:uart.c **** {
457 bic r3, r3, #983040
458 .loc 1 365 0
459 mov r4, #0
460 .loc 1 363 0
461 0314 10402DE9 orr r3, r3, #327680
462 str r3, [lr, #0]
362:uart.c **** // set port pins for UART1
363:uart.c **** PINSEL0 = (PINSEL0 & ~U1_PINMASK) | U1_PINSEL;
463 1 361 0
464 0318 B4E09FE5 mov r0, r0, asl #16
465 031c 00309EE5 .LVL33:
364:uart.c ****
365:uart.c **** U1IER = 0x00; // disable all interrupts
466 oc 1 365 0
467 0320 B0C09FE5 strb r4, [ip, #4]
468 .loc 1 361 0
469 0324 0F38C3E3 mov lr, r0, lsr #16
470 .LVL34:
471 0328 0040A0E3 .loc 1 366 0
472 ldrb r3, [ip, #8] @ zero_extendqisi2
473 032c 053883E3 .loc 1 361 0
474 0330 00308EE5 and r2, r2, #255
475 .loc 1 367 0
476 0334 0008A0E1 ldrb r3, [ip, #0] @ zero_extendqisi2
477 .loc 1 372 0
478 and lr, lr, #255
479 0338 0440CCE5 .LVL35:
480 .loc 1 368 0
481 033c 20E8A0E1 ldrb r3, [ip, #20] @ zero_extendqisi2
482 .loc 1 373 0
366:uart.c **** U1IIR; // clear interrupt ID
483 #24
484 0340 0830DCE5 .loc 1 371 0
485 mvn r3, #127
486 0344 FF2002E2 .loc 1 377 0
367:uart.c **** U1RBR; // clear receive register
487 r1, r1, #127
488 0348 0030DCE5 .LVL36:
368:uart.c **** U1LSR; // clear line status register
369:uart.c ****
370:uart.c **** // set the baudrate
371:uart.c **** U1LCR = ULCR_DLAB_ENABLE; // select divisor latches
372:uart.c **** U1DLL = (uint8_t)baud; // set for baud low byte
489 loc 1 371 0
490 034c FFE00EE2 strb r3, [ip, #12]
491 .loc 1 372 0
492 strb lr, [ip, #0]
493 0350 1430DCE5 .loc 1 373 0
373:uart.c **** U1DLM = (uint8_t)(baud >> 8); // set for baud high byte
494 r0, [ip, #4]
495 0354 200CA0E1 .loc 1 377 0
496 strb r1, [ip, #12]
497 0358 7F30E0E3 .loc 1 378 0
374:uart.c ****
375:uart.c **** // set the number of characters and other
376:uart.c **** // user specified operating parameters
377:uart.c **** U1LCR = (mode & ~ULCR_DLAB_ENABLE);
498 b r2, [ip, #8]
499 035c 7F1001E2 .loc 1 382 0
500 ldr r2, .L56+8
501 .LVL37:
502 0360 0C30CCE5 ldr r3, [r2, #12]
503 bic r3, r3, #128
504 0364 00E0CCE5 str r3, [r2, #12]
505 .loc 1 383 0
506 0368 0400CCE5 mov r3, #128
507 str r3, [r2, #16]
508 036c 0C10CCE5 .loc 1 384 0
378:uart.c **** U1FCR = fmode;
509 9
510 0370 0820CCE5 str r3, [r2, #516]
379:uart.c ****
380:uart.c **** #if defined(UART1_TX_INT_MODE) || defined(UART1_RX_INT_MODE)
381:uart.c **** // initialize the interrupt vector
382:uart.c **** VICIntSelect &= ~VIC_BIT(VIC_UART1); // UART1 selected as IRQ
511 loc 1 385 0
512 0374 60209FE5 ldr r3, .L56+12
513 str r3, [r2, #260]
514 0378 0C3092E5 .loc 1 397 0
515 037c 8030C3E3 ldrb r3, [ip, #4] @ zero_extendqisi2
516 0380 0C3082E5 .loc 1 394 0
383:uart.c **** VICIntEnable = VIC_BIT(VIC_UART1); // UART1 interrupt enabled
517 2, .L56+16
518 0384 8030A0E3 .loc 1 397 0
519 0388 103082E5 orr r3, r3, #1
384:uart.c **** VICVectCntl1 = VIC_ENABLE | VIC_UART1;
520 oc 1 394 0
521 038c 2730A0E3 strh r4, [r2, #0] @ movhi
522 0390 043282E5 .loc 1 397 0
385:uart.c **** VICVectAddr1 = (uint32_t)uart1ISR; // address of the ISR
523 rb r3, [ip, #4]
524 0394 44309FE5 .loc 1 388 0
525 0398 043182E5 ldr r3, .L56+20
386:uart.c ****
387:uart.c **** #ifdef UART1_TX_INT_MODE
388:uart.c **** uart1_tx_extract_idx = uart1_tx_insert_idx = 0;
389:uart.c **** uart1_tx_running = 0;
390:uart.c **** #endif
391:uart.c ****
392:uart.c **** #ifdef UART1_RX_INT_MODE
393:uart.c **** // initialize data queues
394:uart.c **** uart1_rx_extract_idx = uart1_rx_insert_idx = 0;
395:uart.c ****
396:uart.c **** // enable receiver interrupts
397:uart.c **** U1IER |= UIER_ERBFI;
526 rh r4, [r3, #0] @ movhi
527 039c 0430DCE5 ldr r3, .L56+24
528 strh r4, [r3, #0] @ movhi
529 03a0 3C209FE5 .loc 1 389 0
530 ldr r3, .L56+28
531 03a4 013083E3 str r4, [r3, #0]
532 .loc 1 394 0
533 03a8 B040C2E1 ldr r3, .L56+32
534 strh r4, [r3, #0] @ movhi
535 03ac 0430CCE5 .loc 1 400 0
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