uart.lst

rtc code for lpc2148

   1              		.file	"uart.c"
   9              	.Ltext0:
  10              		.align	2
  11              		.global	uart0Init
  13              	uart0Init:
  14              	.LFB2:
  15              		.file 1 "uart.c"
   1:uart.c        **** /******************************************************************************
   2:uart.c        ****  *
   3:uart.c        ****  * $RCSfile: $
   4:uart.c        ****  * $Revision: $
   5:uart.c        ****  *
   6:uart.c        ****  * This module provides interface routines to the LPC ARM UARTs.
   7:uart.c        ****  * Copyright 2004, R O SoftWare
   8:uart.c        ****  * No guarantees, warrantees, or promises, implied or otherwise.
   9:uart.c        ****  * May be used for hobby or commercial purposes provided copyright
  10:uart.c        ****  * notice remains intact.
  11:uart.c        ****  *
  12:uart.c        ****  *****************************************************************************/
  13:uart.c        **** #include <limits.h>
  14:uart.c        **** #include "types.h"
  15:uart.c        **** #include "LPC21xx.h"
  16:uart.c        **** #include "uart.h"
  17:uart.c        **** 
  18:uart.c        **** #if defined(UART0_TX_INT_MODE) || defined(UART0_RX_INT_MODE) || \
  19:uart.c        ****     defined(UART1_TX_INT_MODE) || defined(UART1_RX_INT_MODE)
  20:uart.c        **** #include "armVIC.h"
  21:uart.c        **** #include "uartISR.h"
  22:uart.c        **** #endif
  23:uart.c        **** 
  24:uart.c        **** #if UART0_SUPPORT
  25:uart.c        **** #ifdef UART0_RX_INT_MODE
  26:uart.c        **** uint8_t  uart0_rx_buffer[UART0_RX_BUFFER_SIZE];
  27:uart.c        **** uint16_t uart0_rx_insert_idx, uart0_rx_extract_idx;
  28:uart.c        **** #endif
  29:uart.c        **** 
  30:uart.c        **** #ifdef UART0_TX_INT_MODE
  31:uart.c        **** uint8_t  uart0_tx_buffer[UART0_TX_BUFFER_SIZE];
  32:uart.c        **** uint16_t uart0_tx_insert_idx, uart0_tx_extract_idx;
  33:uart.c        **** int      uart0_tx_running;
  34:uart.c        **** #endif
  35:uart.c        **** #endif
  36:uart.c        **** 
  37:uart.c        **** #if UART1_SUPPORT
  38:uart.c        **** #ifdef UART1_RX_INT_MODE
  39:uart.c        **** uint8_t  uart1_rx_buffer[UART1_RX_BUFFER_SIZE];
  40:uart.c        **** uint16_t uart1_rx_insert_idx, uart1_rx_extract_idx;
  41:uart.c        **** #endif
  42:uart.c        **** 
  43:uart.c        **** #ifdef UART1_TX_INT_MODE
  44:uart.c        **** uint8_t  uart1_tx_buffer[UART1_TX_BUFFER_SIZE];
  45:uart.c        **** uint16_t uart1_tx_insert_idx, uart1_tx_extract_idx;
  46:uart.c        **** int      uart1_tx_running;
  47:uart.c        **** #endif
  48:uart.c        **** #endif
  49:uart.c        **** 
  50:uart.c        **** #if UART0_SUPPORT
  51:uart.c        **** 
  52:uart.c        **** /******************************************************************************
  53:uart.c        ****  *
  54:uart.c        ****  * Function Name: uart0Init()
  55:uart.c        ****  *
  56:uart.c        ****  * Description:  
  57:uart.c        ****  *    This function initializes the UART for async mode
  58:uart.c        ****  *
  59:uart.c        ****  * Calling Sequence: 
  60:uart.c        ****  *    baudrate divisor - use UART_BAUD macro
  61:uart.c        ****  *    mode - see typical modes (uart.h)
  62:uart.c        ****  *    fmode - see typical fmodes (uart.h)
  63:uart.c        ****  *
  64:uart.c        ****  * Returns:
  65:uart.c        ****  *    void
  66:uart.c        ****  *
  67:uart.c        ****  * NOTE: uart0Init(UART_BAUD(9600), UART_8N1, UART_FIFO_8);
  68:uart.c        ****  *
  69:uart.c        ****  *****************************************************************************/
  70:uart.c        **** void uart0Init(uint16_t baud, uint8_t mode, uint8_t fmode)
  71:uart.c        **** {
  16              	 args = 0, pretend = 0, frame = 0
  17              		@ frame_needed = 0, uses_anonymous_args = 0
  18              	.LVL0:
  19              		stmfd	sp!, {r4, lr}
  20 0000 10402DE9 	.LCFI0:
  21              		.loc 1 73 0
  72:uart.c        ****   // set port pins for UART0
  73:uart.c        ****   PINSEL0 = (PINSEL0 & ~U0_PINMASK) | U0_PINSEL;
  22              	r, .L3
  23 0004 B0E09FE5 		ldr	r3, [lr, #0]
  24 0008 00309EE5 		.loc 1 75 0
  74:uart.c        **** 
  75:uart.c        ****   U0IER = 0x00;                         // disable all interrupts
  25              	r	ip, .L3+4
  26 000c ACC09FE5 		.loc 1 73 0
  27              		bic	r3, r3, #15
  28 0010 0F30C3E3 		.loc 1 75 0
  29              		mov	r4, #0
  30 0014 0040A0E3 		.loc 1 73 0
  31              		orr	r3, r3, #5
  32 0018 053083E3 		str	r3, [lr, #0]
  33 001c 00308EE5 		.loc 1 71 0
  34              		mov	r0, r0, asl #16
  35 0020 0008A0E1 	.LVL1:
  36              		.loc 1 75 0
  37              		strb	r4, [ip, #4]
  38 0024 0440CCE5 		.loc 1 71 0
  39              		mov	lr, r0, lsr #16
  40 0028 20E8A0E1 	.LVL2:
  41              		.loc 1 76 0
  76:uart.c        ****   U0IIR;                                // clear interrupt ID
  42              	]	@ zero_extendqisi2
  43 002c 0830DCE5 		.loc 1 71 0
  44              		and	r2, r2, #255
  45 0030 FF2002E2 		.loc 1 77 0
  77:uart.c        ****   U0RBR;                                // clear receive register
  46              	b	r3, [ip, #0]	@ zero_extendqisi2
  47 0034 0030DCE5 		.loc 1 87 0
  78:uart.c        ****   U0LSR;                                // clear line status register
  79:uart.c        **** 
  80:uart.c        ****   // set the baudrate
  81:uart.c        ****   U0LCR = ULCR_DLAB_ENABLE;             // select divisor latches 
  82:uart.c        ****   U0DLL = (uint8_t)baud;                // set for baud low byte
  83:uart.c        ****   U0DLM = (uint8_t)(baud >> 8);         // set for baud high byte
  84:uart.c        **** 
  85:uart.c        ****   // set the number of characters and other
  86:uart.c        ****   // user specified operating parameters
  87:uart.c        ****   U0LCR = (mode & ~ULCR_DLAB_ENABLE);
  48              	nd	r1, r1, #127
  49 0038 7F1001E2 	.LVL3:
  50              		.loc 1 78 0
  51              		ldrb	r3, [ip, #20]	@ zero_extendqisi2
  52 003c 1430DCE5 		.loc 1 82 0
  53              		and	lr, lr, #255
  54 0040 FFE00EE2 	.LVL4:
  55              		.loc 1 81 0
  56              		mvn	r3, #127
  57 0044 7F30E0E3 		.loc 1 83 0
  58              		mov	r0, r0, lsr #24
  59 0048 200CA0E1 		.loc 1 81 0
  60              		strb	r3, [ip, #12]
  61 004c 0C30CCE5 		.loc 1 82 0
  62              		strb	lr, [ip, #0]
  63 0050 00E0CCE5 		.loc 1 83 0
  64              		strb	r0, [ip, #4]
  65 0054 0400CCE5 		.loc 1 87 0
  66              		strb	r1, [ip, #12]
  67 0058 0C10CCE5 		.loc 1 88 0
  88:uart.c        ****   U0FCR = fmode;
  68              	.loc 1 92 0
  69 005c 0820CCE5 		ldr	r1, .L3+8
  89:uart.c        **** 
  90:uart.c        **** #if defined(UART0_TX_INT_MODE) || defined(UART0_RX_INT_MODE)
  91:uart.c        ****   // initialize the interrupt vector
  92:uart.c        ****   VICIntSelect &= ~VIC_BIT(VIC_UART0);  // UART0 selected as IRQ
  70              	dr	r3, [r1, #12]
  71 0060 5C109FE5 		bic	r3, r3, #64
  72 0064 0C3091E5 		str	r3, [r1, #12]
  73 0068 4030C3E3 		.loc 1 99 0
  74 006c 0C3081E5 		ldr	r3, .L3+12
  93:uart.c        ****   VICIntEnable = VIC_BIT(VIC_UART0);    // UART0 interrupt enabled
  94:uart.c        ****   VICVectCntl0 = VIC_ENABLE | VIC_UART0;
  95:uart.c        ****   VICVectAddr0 = (uint32_t)uart0ISR;    // address of the ISR
  96:uart.c        **** 
  97:uart.c        **** #ifdef UART0_TX_INT_MODE
  98:uart.c        ****   // initialize the transmit data queue
  99:uart.c        ****   uart0_tx_extract_idx = uart0_tx_insert_idx = 0;
  75              		r4, [r3, #0]	@ movhi
  76 0070 50309FE5 		.loc 1 93 0
  77 0074 B040C3E1 		mov	r3, #64
  78              		str	r3, [r1, #16]
  79 0078 4030A0E3 		.loc 1 99 0
  80 007c 103081E5 		ldr	r3, .L3+16
  81              		strh	r4, [r3, #0]	@ movhi
  82 0080 44309FE5 		.loc 1 94 0
  83 0084 B040C3E1 		mov	r3, #38
  84              		str	r3, [r1, #512]
  85 0088 2630A0E3 		.loc 1 95 0
  86 008c 003281E5 		ldr	r3, .L3+20
  87              		.loc 1 105 0
  88 0090 38309FE5 		ldr	r2, .L3+24
 100:uart.c        ****   uart0_tx_running = 0;
 101:uart.c        **** #endif
 102:uart.c        **** 
 103:uart.c        **** #ifdef UART0_RX_INT_MODE
 104:uart.c        ****   // initialize the receive data queue
 105:uart.c        ****   uart0_rx_extract_idx = uart0_rx_insert_idx = 0;
  89              	 95 0
  90 0094 38209FE5 		str	r3, [r1, #256]
  91              		.loc 1 108 0
  92              		mov	r3, #1
  93 0098 003181E5 		.loc 1 105 0
 106:uart.c        **** 
 107:uart.c        ****   // enable receiver interrupts
 108:uart.c        ****   U0IER = UIER_ERBFI;
  94              		r4, [r2, #0]	@ movhi
  95 009c 0130A0E3 		.loc 1 108 0
  96              		strb	r3, [ip, #4]
  97 00a0 B040C2E1 		.loc 1 100 0
  98              		ldr	r3, .L3+28
  99 00a4 0430CCE5 		str	r4, [r3, #0]
 100              		.loc 1 105 0
 101 00a8 28309FE5 		ldr	r3, .L3+32
 102 00ac 004083E5 		strh	r4, [r3, #0]	@ movhi
 103              		.loc 1 111 0
 104 00b0 24309FE5 		ldmfd	sp!, {r4, pc}
 105 00b4 B040C3E1 	.L4:
 109:uart.c        **** #endif
 110:uart.c        **** #endif
 111:uart.c        **** }
 106              	3:
 107 00b8 1080BDE8 		.word	-536690688
 108              		.word	-536821760
 109              		.word	-4096
 110              		.word	uart0_tx_insert_idx
 111 00bc 00C002E0 		.word	uart0_tx_extract_idx
 112 00c0 00C000E0 		.word	uart0ISR
 113 00c4 00F0FFFF 		.word	uart0_rx_extract_idx
 114 00c8 00000000 		.word	uart0_tx_running
 115 00cc 00000000 		.word	uart0_rx_insert_idx
 116 00d0 00000000 	.LFE2:
 118 00d8 00000000 		.align	2
 119 00dc 00000000 		.global	uart0Putch
 121              	uart0Putch:
 122              	.LFB3:
 123              		.loc 1 129 0
 124              		@ args = 0, pretend = 0, frame = 0
 125              		@ frame_needed = 0, uses_anonymous_args = 0
 126              	.LVL6:
 112:uart.c        **** 
 113:uart.c        **** /******************************************************************************
 114:uart.c        ****  *
 115:uart.c        ****  * Function Name: uart0Putch()
 116:uart.c        ****  *
 117:uart.c        ****  * Description:  
 118:uart.c        ****  *    This function puts a character into the UART output queue for
 119:uart.c        ****  *    transmission.
 120:uart.c        ****  *
 121:uart.c        ****  * Calling Sequence: 
 122:uart.c        ****  *    character to be transmitted
 123:uart.c        ****  *
 124:uart.c        ****  * Returns:
 125:uart.c        ****  *    ch on success, -1 on error (queue full)
 126:uart.c        ****  *
 127:uart.c        ****  *****************************************************************************/
 128:uart.c        **** int uart0Putch(int ch)
 129:uart.c        **** {
 127              	r6, r7, lr}
 128              	.LCFI1:
 129              		.loc 1 134 0
 130              		ldr	r6, .L14
 131 00e0 F0402DE9 		ldrh	r3, [r6, #0]
 132              		ldr	r2, .L14+4
 130:uart.c        **** #ifdef UART0_TX_INT_MODE
 131:uart.c        ****   uint16_t temp;
 132:uart.c        ****   unsigned cpsr;
 133:uart.c        **** 
 134:uart.c        ****   temp = (uart0_tx_insert_idx + 1) % UART0_TX_BUFFER_SIZE;
 133              	3, r3, #1
 134 00e4 94609FE5 		and	r2, r3, r2
 135 00e8 B030D6E1 		.loc 1 136 0
 136 00ec 90209FE5 		ldr	r3, .L14+8
 137 00f0 013083E2 		.loc 1 134 0
 138 00f4 022003E0 		mov	r2, r2, asl #16
 135:uart.c        **** 
 136:uart.c        ****   if (temp == uart0_tx_extract_idx)
 139              	1 136 0
 140 00f8 88309FE5 		ldrh	r3, [r3, #0]
 141              		.loc 1 134 0
 142 00fc 0228A0E1 		mov	r5, r2, lsr #16
 143              	.LVL7:
 144 0100 B030D3E1 		.loc 1 136 0
 145              		cmp	r3, r5
 146 0104 2258A0E1 		.loc 1 140 0
 147              		ldr	r7, .L14+12
 148              		.loc 1 136 0
 149 0108 050053E1 		mvn	r3, #0
 137:uart.c        ****     return -1;                          // no room
 138:uart.c        **** 
 139:uart.c        ****   cpsr = disableIRQ();                  // disable global interrupts
 140:uart.c        ****   U0IER &= ~UIER_ETBEI;                 // disable TX interrupts
 150              	 0
 151 010c 78709FE5 		mov	r4, r0
 152              		.loc 1 136 0
 153 0110 0030E0E3 		beq	.L9
 154              	.LVL8:
 155 0114 0040A0E1 		.loc 1 139 0
 156              		bl	disableIRQ
 157 0118 1600000A 		.loc 1 140 0
 158              		ldrb	r3, [r7, #4]	@ zero_extendqisi2
 159              		and	r3, r3, #253
 160 011c FEFFFFEB 		strb	r3, [r7, #4]
 161              		.loc 1 141 0
 162 0120 0430D7E5 		bl	restoreIRQ
 163 0124 FD3003E2 		.loc 1 144 0
 164 0128 0430C7E5 		ldr	r1, .L14+16
 141:uart.c        ****   restoreIRQ(cpsr);                     // restore global interrupts
 165              	0]
 166 012c FEFFFFEB 		cmp	r3, #0
 142:uart.c        **** 
 143:uart.c        ****   // check if in process of sending data
 144:uart.c        ****   if (uart0_tx_running)
 167              	loc 1 154 0
 168 0130 58109FE5 		and	r2, r4, #255
 169 0134 003091E5 		.loc 1 147 0