lpc2478_config.h

I2c code for LPC2148

#define BIT(n)      	(1L << (n))
#define nBIT(n)			(!BIT(n))

#define PCTimer0	 BIT(1)
#define PCTimer1	 BIT(2)
#define PCUART0		 BIT(3)
#define PCUART1		 BIT(4)
#define PCPWM0		 BIT(5)
#define PCPWM1		 BIT(6)
#define PCI2C0		 BIT(7)
#define PCSPI		 BIT(8)
#define PCRTC		 BIT(9)
#define PCSSP1		 BIT(10)
#define PCEMC		 BIT(11)
#define PCAD		nBIT(12)
#define PCCAN1		nBIT(13)
#define PCCAN2		nBIT(14)
#define PCI2C1		 BIT(19)
#define PCLCD		nBIT(20)
#define PCSSP0		 BIT(21)
#define PCTIM2		nBIT(22)
#define PCTIM3		nBIT(23)
#define PCUART2		nBIT(24)
#define PCUART3		nBIT(25)
#define PCI2C2		 BIT(26)
#define PCI2S		nBIT(27)
#define PCSDC		nBIT(28)
#define PCGPDMA		nBIT(29)
#define PCENET		nBIT(30)
#define PCUSB		nBIT(31)


#define I2CONSET_AA			0x00000004
#define I2CONSET_SI			0x00000008
#define I2CONSET_STO		0x00000010
#define I2CONSET_STA		0x00000020
#define I2CONSET_I2EN		0x00000040  						/* I2C Control Set Register */

#define I2CONCLR_AAC		0x00000004  /* I2C Control clear Register */
#define I2CONCLR_SIC		0x00000008
#define I2CONCLR_STAC		0x00000020
#define I2CONCLR_I2ENC		0x00000040

/* ------ I2C STATUS CODES: MASTER IN Transmit MODE ------- */
#define  I2STAT_SLA_W_ACK               0x18
#define  I2STAT_SLA_W_NOACK             0x20
#define  I2STAT_DAT_T_ACK               0x28
#define  I2STAT_DAT_T_NOACK             0x30

/* ------ I2C STATUS CODES: MASTER IN RECEIVER MODE ------- */
#define  I2STAT_SLA_R_ACK               0x40
#define  I2STAT_SLA_R_NOACK             0x48
#define  I2STAT_DAT_R_ACK               0x50
#define  I2STAT_DAT_R_NOACK             0x58

/* ---------- I2C STATUS CODES: MASTER AND SLAVE ---------- */
#define  I2STAT_START                   0x08
#define  I2STAT_REPEATED_START          0x10
#define  I2STAT_ARB_LOST                0x38
#define  I2STAT_NOP                     0x58
#define  I2STAT_BUS_ERROR               0x00


#define I2CMASTER		0x01
#define I2CSLAVE		0x02


#define I2C0PIN_MASK		0xFC3FFFFF
#define I2C0PIN_SELECT		0x01400000

#define I2CSCLH 			0xB4
#define I2CSCLL				0xB4



 /*
Important information of i2c
From the LPC2148 User Manual section 11.7.8:

I2C Bit Frequency = PCLK / (I2CSCLH + I2CSCLL)

PCLK is whatever you set it to when you set up when you set up VPBDIV
but that is based on CCLK which is set to some multiple of the crystal
frequency when you set up PLL0.

So, maybe the crystal is 12 MHz and the PLL multiplies by 5 so CCLK is
60 MHz. Then maybe VPBDIV is set to divide by 4 (if that is what you
want; it can divide by 1, 2 or 4) so PCLK is 15 MHz.

Now, maybe you want 100 kHz for the I2C bit frequency (slow I2C) so:

100,000 = (15000000) / (I2CSCLH + I2CSCLL)

400,000 = (30000000) / (I2CSCLH + I2CSCLL)

Then I2CSCLH + I2CSCLL = 30000000 / 400000 or 75.

100,000 = (30000000) / (I2CSCLH + I2CSCLL)

Then I2CSCLH + I2CSCLL = 30000000 / 100000 or 300.

ex.
    crystal is 12MHZ pll mulitiply by 6 so cclk is 72MHz.
	Now VPBDIV is set to 2 so PCLK is 36MHz

	we want to run i2c on 100 KHz 
	100,000= (36000000)/(I2CSCLH + I2CSCLL)
	I2CSCLH + I2CSCLL = 36000000 / 100000 = 360
						36000000 / 400000 = 90
	50% dutycycle I2CSCLH = 180 & I2CSCLL = 180

Then is no reason the 2 values aren't the same so set them both for 75
to get 50% duty cycle on the clock. For a 400 kHz I2C, you need to
read the I2C spec to get the proper duty cycle. Google for it.

It all ties together but you have to start with crystal freq -> PLL
multiplication to get CCLK -> VPBDIV to get PCLK -> desired I2C clock
rate to get (I2CSCLH + I2CSCLL) -> I2C Spec to get the required duty
cycle if the I2C bit rate is not 100 kHz.
*/