📄 frequency.c
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// Reserved (bits 15-1)
// SWSM (bit 0) - 1 wait-state base values are mulitplied by 2
// for a maximum of 14 wait states.
// --------------------------
// 0000 0000 0000 0001
//--------------------------------------------------------------------
*(unsigned int*)SWCR=0x0001;
//--------------------------------------------------------------------
//BSCR DEFINITIONS?
// BNKCMP (bit 15-12) - 1111 Bank compare. Determines the external memory-bank size. BNKCMP is used to mask the four MSBs of
// an address.
// 1111 4k
// 1110 8k
// 1100 16k
// 1000 32k
// 0000 64k
// PS-DS (bit 11) - 1 One extra cycle is inserted between consecutive data and program reads.
// Reserved (bits 10-3) - 00000000
// HBH (bit 2) - 0 The hpi bus holder is disabled
// BH (bit 1) - 0 The data bus holder is disabled
// EXIO (bit 0) - 0 The external bus interface functions as usual
// ------------------------------------
// 1111 1000 0000 0000
//--------------------------------------------------------------------
*(unsigned int*)BSCR=0xf800;
//--------------------------------------------------------------------
asm(" ssbx intm "); //Disable all mask interrupts
//--------------------------------------------------------------------
// IMR DEFINITIONS
// Writing a 1 to any IMR bit position enables the corresponding interrupt (when INTM = 0)
// Reserved (bits 15-14) - xx
// DMAC5 (bit 13) - 0 DMA channel 5 interrupt mask bit
// DMAC4 (bit 12) - 0 DMA channel 4 interrupt mask bit
// BXINT1/DMAC3 (bit 11) - 0 McBSP1 transmit interrupt mask bit, or the DMA channel 3
// BRINT1/DMAC2 (bit 10) - 0 McBSP1 receive interrupt mask bit, or the DMA channel 2
// HPINT (bit 9) - 0 Host to ’54x interrup /mask
// INT3 (bit 8) - 0 External interrupt 3 mask
// TINT1/DMAC1 (bit 7) - 0 timer1 interrupt mask bit, or the DMA channel 1 interrupt mask bit
// DMAC0 (bit 6) - 0 reserved, or the DMA channel 0 interrupt mask bit
// BXINT0 (bit 5) - 0 McBSP0 transmit interrupt mask bit
// BRINT0 (bit 4) - 0 McBSP0 receive interrupt mask bit
// TINT0 (bit 3) - 0 Timer 0 interrupt mask bit
// INT2 (bit 2) - 0 External interrupt 2 mask bit
// INT1 (bit 1) - 0 External interrupt 1 mask bit
// INT0 (bit 0) - 0 External interrupt 0 mask bit
// ------------------------------
// 0000 0000 0000 0000
//--------------------------------------------------------------------
*(unsigned int*)IMR=0x0;
//--------------------------------------------------------------------
// IFR DEFINITIONS
// Writing a 1 to any IFR bit position clear the corresponding interrupt mask ,when corresponding interrupt occur IFR corresponding bit=1
// Reserved (bits 15-14) - xx
// DMAC5 (bit 13) - 1 DMA channel 5 interrupt flag bit
// DMAC4 (bit 12) - 1 DMA channel 4 interrupt flag bit
// BXINT1/DMAC3 (bit 11) - 1 McBSP1 transmit interrupt flag bit, or the DMA channel 3
// BRINT1/DMAC2 (bit 10) - 1 McBSP1 receive interrupt flag bit, or the DMA channel 2
// HPINT (bit 9) - 1 Host to ’54x interrutpflak
// INT3 (bit 8) - 1 External interrupt 3 flag
// TINT1/DMAC1 (bit 7) - 1 timer1 interrupt flag bit, or the DMA channel 1 interrupt mask bit
// DMAC0 (bit 6) - 1 reserved, or the DMA channel 0 interrupt flag bit
// BXINT0 (bit 5) - 1 McBSP0 transmit interrupt flag bit
// BRINT0 (bit 4) - 1 McBSP0 receive interrupt flag bit
// TINT0 (bit 3) - 1 Timer 0 interrupt flag bit
// INT2 (bit 2) - 1 External interrupt 2 flag bit
// INT1 (bit 1) - 1 External interrupt 1 flag bit
// INT0 (bit 0) - 1 External interrupt 0 flag bit
// ------------------------------
// 1111 1111 1111 1111
//--------------------------------------------------------------------
*(unsigned int*)IFR=0xffff;
//--------------------------------------------------------------------
asm(" nop ");
asm(" nop ");
asm(" nop ");
}
//--------------------------------------------------------------------
/*
*************************************************************************
- 函数名称 : void aic23_init(void)
- 函数说明 : 初始化AIC23
- 输入参数 : 无
- 输出参数 : 无
- 补充说明 :
**************************************************************************
*/
void aic23_init(void)
{
mcbsp0_write_rdy(0x1e00); //REG10 RESET AIC23
asm(" nop "); //Address (bits 15-9) 0001111
//RES (bits 8-0) 000000000
//-----0001 1110 0000 0000
mcbsp0_write_rdy(0x0117); //REG0 Left line input channel volume control
asm(" nop "); //Address (bits 15-9) 0000000
//LRS (bits 8) 1 Left/right line simultaneous volume/mute update Enabled
//LIM (bits 7) 0 Left line input mute 0 = Normal
//XX (bits 6-5) 00 Reserved
//LIV[4:0] (bits 4-0) 10111 Left line input volume control (10111 = 0 dB default)
//-----0000 0001 0001 0111
mcbsp0_write_rdy(0x0317); //REG1 Right Line Input Channel Volume Control
asm(" nop "); //Address (bits 15-9) 0000001
//RRS (bits 8) 1 Left/right line simultaneous volume/mute update Enabled
//RIM (bits 7) 0 Left line input mute 0 = Normal
//XX (bits 6-5) 00 Reserved
//RIV[4:0] (bits 4-0) 10111 Left line input volume control (10111 = 0 dB default)
//-----0000 0011 0001 0111
mcbsp0_write_rdy(0x05f9); //REG2 Left Channel Headphone Volume Control
asm(" nop "); //Address (bits 15-9) 0000010
//LRS (bits 8) 1 Left/right headphone channel simultaneous volume/mute update 1 = Enabled
//LZC (bits 7) 1 Left-channel zero-cross detect 0 = Off
//LHV[6:0] (bits 6-0) 1111001 Left Headphone volume control (1111001 = 0 dB default)
//-----0000 0101 1111 1001
mcbsp0_write_rdy(0x07f9); //REG3 Right Channel Headphone Volume Control
asm(" nop "); //Address (bits 15-9) 0000011
//RLS (bits 8) 1 Left/right headphone channel simultaneous volume/mute update 1 = Enabled
//RZC (bits 7) 1 Left-channel zero-cross detect 0 = Off
//RHV[6:0] (bits 6-0) 1111001 Left Headphone volume control (1111001 = 0 dB default)
//-----0000 0111 1111 1001
// mcbsp0_write_rdy(0x0810); //选择线性输入
mcbsp0_write_rdy(0x0814); //选择麦克风输入
asm(" nop "); //REG4 Analog Audio Path Control
//Address (bits 15-9) 0000100
//X (bits 8) 0 Reserved
//STA[1:0] (bits 7-6) 00 Sidetone attenuation 00 = –6 dB
//STE (bits 5) 0 Sidetone enable 0 = Disabled
//DAC (bits 4) 1 DAC select 1 = DAC selected
//BYP (bits 3) 0 Bypass 0 = Disabled 1=Enabled,ONLY FOR TEST
//INSEL (bits 2) 0 Input select for ADC 0 = Line
//MICM (bits 1) 0 Microphone mute 0 = Normal
//MICB (bits 0) 0 Microphone boost 0=OdB
//-----0000 1000 0001 0000
mcbsp0_write_rdy(0x0A01); //REG5 Digital Audio Path Control
asm(" nop "); //Address (bits 15-9) 0000101
//X (bits 8-4) 00000 Reserved
//DACM (bits 3) 0 DAC soft mute 0 = Disabled
//DEEMP[1:0] (bits 2-1) 00 De-emphasis control 00 = Disabled
//ADCHP (bits 0) 1 ADC high-pass filter 1 = Enabled
//----- 0000 1010 0000 0001
mcbsp0_write_rdy(0x0C00); //REG6 Power Down Control
asm(" nop "); //Address (bits 15-9) 0000110
//X (bits 8) 0 Reserved
//OFF (bits 7) 0 Device power 0 = On
//CLK (bits 6) 0 Clock 0 = On
//OSC (bits 5) 0 Oscillator 0 = On
//OUT (bits 4) 0 Outputs 0 = On
//DAC (bits 3) 0 DAC 0 = On
//ADC (bits 2) 0 ADC 0 = On
//MIC (bits 1) 0 Microphone input 0 = On
//LINE (bits 0) 0 Line input 0 = On
//----- 0000 1100 0000 0000
mcbsp0_write_rdy(0x0E73); //REG7 Digital Audio Interface Format
asm(" nop "); //Address (bits 15-9) 0000111
//X (bits 8-7) 00 Reserved
//MS (bits 6) 1 Master/slave mode 1 = Master
//LRSWAP (bits 5) 1 DAC left/right swap 1 = Enabled
//LRP (bits 4) 1 DAC left/right phase,1 = Right channel on, LRCIN low; "DSP mode", 1 = MSB is available on 2nd BCLK rising edge after LRCIN rising edge
//IWL[1:0] (bits 3-2) 00 Input bit length 00 = 16 bit
//FOR[1:0] (bits 1-0) 11 Data format 11 = DSP format, frame sync followed by two data words
//----- 0000 1110 0111 0011
mcbsp0_write_rdy(0x100C); //8KHZ采样频率
//mcbsp0_write_rdy(0x101C); //96KHZ采样频率
//REG8 Sample Rate Control
asm(" nop "); //Address (bits 15-9) 0001000
//X (bits 8) 0 Reserved
//CLKOUT (bits 7) 0 Clock input divider 0 = MCLK
//CLKIN (bits 6) 0 Clock output divider 0 = MCLK
//SR[3:0] (bits 5-2) 0011 MCLK = 12.288 MHz, sampling rates=8KHZ
//BOSR (bits 1) 0 Base oversampling rate Normal mode: 0 = 256 fs
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