lock.rpt

四位密码锁

-- Node name is ':2706' 
-- Equation name is '_LC8_A20', type is buried 
_LC8_A20 = LCELL( _EQ068);
  _EQ068 = !b4 & !b7 &  _LC7_A20
         # !b4 & !_LC5_A20;

-- Node name is ':2716' 
-- Equation name is '_LC4_A20', type is buried 
_LC4_A20 = LCELL( _EQ069);
  _EQ069 = !b1 &  _LC8_A20
         # !b1 & !_LC1_A17
         # !_LC1_A16;

-- Node name is '~2740~1' 
-- Equation name is '~2740~1', location is LC3_A17, type is buried.
-- synthesized logic cell 
_LC3_A17 = LCELL( _EQ070);
  _EQ070 =  b9
         #  b8
         # !_LC2_A17
         #  b3;

-- Node name is ':2752' 
-- Equation name is '_LC5_A17', type is buried 
_LC5_A17 = LCELL( _EQ071);
  _EQ071 = !b2 &  _LC5_A17
         # !b2 &  _LC3_A17
         # !_LC1_A13;

-- Node name is ':2764' 
-- Equation name is '_LC6_A20', type is buried 
_LC6_A20 = LCELL( _EQ072);
  _EQ072 =  _LC1_A20
         #  b9
         #  b8
         #  b7;

-- Node name is '~2788~1' 
-- Equation name is '~2788~1', location is LC1_A21, type is buried.
-- synthesized logic cell 
!_LC1_A21 = _LC1_A21~NOT;
_LC1_A21~NOT = LCELL( _EQ073);
  _EQ073 =  _LC1_A13 &  _LC1_A17;

-- Node name is ':2788' 
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = LCELL( _EQ074);
  _EQ074 =  _LC5_A20 &  _LC6_A20
         #  b4
         #  _LC1_A21;

-- Node name is '~2800~1' 
-- Equation name is '~2800~1', location is LC2_A20, type is buried.
-- synthesized logic cell 
!_LC2_A20 = _LC2_A20~NOT;
_LC2_A20~NOT = LCELL( _EQ075);
  _EQ075 = !b8 & !b9;

-- Node name is ':2800' 
-- Equation name is '_LC6_A13', type is buried 
_LC6_A13 = LCELL( _EQ076);
  _EQ076 =  _LC8_A13
         #  b9
         #  b8
         #  b7;

-- Node name is ':2814' 
-- Equation name is '_LC7_A13', type is buried 
_LC7_A13 = LCELL( _EQ077);
  _EQ077 = !b4 & !b6 &  _LC6_A13
         # !b4 &  b5;

-- Node name is ':2824' 
-- Equation name is '_LC8_A13', type is buried 
_LC8_A13 = LCELL( _EQ078);
  _EQ078 = !b1 &  _LC7_A13
         # !b1 & !_LC1_A17
         # !_LC1_A16;

-- Node name is ':2889' 
-- Equation name is '_LC3_B3', type is buried 
!_LC3_B3 = _LC3_B3~NOT;
_LC3_B3~NOT = LCELL( _EQ079);
  _EQ079 = !en
         # !_LC5_B3
         #  _LC6_B3;

-- Node name is ':2985' 
-- Equation name is '_LC5_C1', type is buried 
_LC5_C1  = LCELL( _EQ080);
  _EQ080 =  _LC3_B3 &  _LC3_C9
         # !_LC3_B3 &  _LC5_C1;

-- Node name is ':2991' 
-- Equation name is '_LC4_C1', type is buried 
_LC4_C1  = LCELL( _EQ081);
  _EQ081 =  _LC2_C9 &  _LC3_B3
         # !_LC3_B3 &  _LC4_C1;

-- Node name is ':2997' 
-- Equation name is '_LC7_C1', type is buried 
_LC7_C1  = LCELL( _EQ082);
  _EQ082 =  _LC3_B3 &  _LC5_C8
         # !_LC3_B3 &  _LC7_C1;

-- Node name is ':3003' 
-- Equation name is '_LC6_C1', type is buried 
_LC6_C1  = LCELL( _EQ083);
  _EQ083 =  _LC2_C11 &  _LC3_B3
         # !_LC3_B3 &  _LC6_C1;

-- Node name is ':3009' 
-- Equation name is '_LC8_A14', type is buried 
_LC8_A14 = LCELL( _EQ084);
  _EQ084 =  _LC3_B3 &  _LC7_A14
         # !_LC3_B3 &  _LC8_A14;

-- Node name is ':3015' 
-- Equation name is '_LC5_A14', type is buried 
_LC5_A14 = LCELL( _EQ085);
  _EQ085 =  _LC3_A14 &  _LC3_B3
         # !_LC3_B3 &  _LC5_A14;

-- Node name is ':3021' 
-- Equation name is '_LC3_A15', type is buried 
_LC3_A15 = LCELL( _EQ086);
  _EQ086 =  _LC3_A13 &  _LC3_B3
         #  _LC3_A15 & !_LC3_B3;

-- Node name is ':3027' 
-- Equation name is '_LC1_A15', type is buried 
_LC1_A15 = LCELL( _EQ087);
  _EQ087 =  _LC1_A19 &  _LC3_B3
         #  _LC1_A15 & !_LC3_B3;

-- Node name is '~3119~1' 
-- Equation name is '~3119~1', location is LC2_C1, type is buried.
-- synthesized logic cell 
_LC2_C1  = LCELL( _EQ088);
  _EQ088 =  _LC2_C9 &  _LC3_C9 &  _LC4_C1 &  _LC5_C1
         #  _LC2_C9 & !_LC3_C9 &  _LC4_C1 & !_LC5_C1
         # !_LC2_C9 &  _LC3_C9 & !_LC4_C1 &  _LC5_C1
         # !_LC2_C9 & !_LC3_C9 & !_LC4_C1 & !_LC5_C1;

-- Node name is '~3119~2' 
-- Equation name is '~3119~2', location is LC3_C1, type is buried.
-- synthesized logic cell 
_LC3_C1  = LCELL( _EQ089);
  _EQ089 =  _LC2_C11 &  _LC5_C8 &  _LC6_C1 &  _LC7_C1
         #  _LC2_C11 & !_LC5_C8 &  _LC6_C1 & !_LC7_C1
         # !_LC2_C11 &  _LC5_C8 & !_LC6_C1 &  _LC7_C1
         # !_LC2_C11 & !_LC5_C8 & !_LC6_C1 & !_LC7_C1;

-- Node name is '~3119~3' 
-- Equation name is '~3119~3', location is LC1_A14, type is buried.
-- synthesized logic cell 
_LC1_A14 = LCELL( _EQ090);
  _EQ090 =  _LC3_A14 &  _LC5_A14 &  _LC7_A14 &  _LC8_A14
         #  _LC3_A14 &  _LC5_A14 & !_LC7_A14 & !_LC8_A14
         # !_LC3_A14 & !_LC5_A14 &  _LC7_A14 &  _LC8_A14
         # !_LC3_A14 & !_LC5_A14 & !_LC7_A14 & !_LC8_A14;

-- Node name is '~3119~4' 
-- Equation name is '~3119~4', location is LC2_A15, type is buried.
-- synthesized logic cell 
_LC2_A15 = LCELL( _EQ091);
  _EQ091 =  _LC1_A15 &  _LC1_A19 &  _LC3_A13 &  _LC3_A15
         #  _LC1_A15 &  _LC1_A19 & !_LC3_A13 & !_LC3_A15
         # !_LC1_A15 & !_LC1_A19 &  _LC3_A13 &  _LC3_A15
         # !_LC1_A15 & !_LC1_A19 & !_LC3_A13 & !_LC3_A15;

-- Node name is '~3119~5' 
-- Equation name is '~3119~5', location is LC4_B3, type is buried.
-- synthesized logic cell 
_LC4_B3  = LCELL( _EQ092);
  _EQ092 =  enl &  _LC1_C1 & !_LC7_B3;

-- Node name is ':3119' 
-- Equation name is '_LC1_C1', type is buried 
_LC1_C1  = LCELL( _EQ093);
  _EQ093 =  _LC1_A14 &  _LC2_A15 &  _LC2_C1 &  _LC3_C1;

-- Node name is ':3176' 
-- Equation name is '_LC8_B3', type is buried 
_LC8_B3  = LCELL( _EQ094);
  _EQ094 = !enl &  _LC1_B3
         #  _LC1_B3 &  _LC7_B3;

-- Node name is '~3193~1' 
-- Equation name is '~3193~1', location is LC2_B3, type is buried.
-- synthesized logic cell 
_LC2_B3  = LCELL( _EQ095);
  _EQ095 =  enl & !_LC1_C1 & !_LC7_B3;

-- Node name is ':3219' 
-- Equation name is '_LC7_B3', type is buried 
_LC7_B3  = LCELL( _EQ096);
  _EQ096 =  enl
         #  en &  _LC7_B3;

-- Node name is ':3225' 
-- Equation name is '_LC1_B3', type is buried 
_LC1_B3  = LCELL( _EQ097);
  _EQ097 =  en &  _LC8_B3
         #  enl &  _LC8_B3
         #  en &  _LC4_B3
         #  enl &  _LC4_B3;

-- Node name is ':3231' 
-- Equation name is '_LC5_B3', type is buried 
_LC5_B3  = LCELL( _EQ098);
  _EQ098 =  en &  _LC5_B3
         #  en &  _LC4_B3
         #  enl &  _LC5_B3
         #  enl &  _LC4_B3;

-- Node name is ':3237' 
-- Equation name is '_LC4_B12', type is buried 
_LC4_B12 = LCELL( _EQ099);
  _EQ099 =  en &  _LC4_B12
         #  enl &  _LC4_B12
         #  en &  _LC2_B3
         #  enl &  _LC2_B3;

-- Node name is ':3255' 
-- Equation name is '_LC6_B3', type is buried 
_LC6_B3  = LCELL( _EQ100);
  _EQ100 =  en &  _LC5_B3
         #  en &  _LC6_B3
         #  enl & !_LC5_B3 &  _LC6_B3;



Project Information                                  d:\maxplus\shuzi\lock.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 16,666K