📄 lock.rpt
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- 6 - C 09 AND2 s ! 0 2 0 3 ~1393~1
- 1 - C 09 OR2 1 3 1 1 :1393
- 1 - C 03 AND2 s ! 2 0 0 7 ~1405~1
- 8 - C 08 OR2 1 2 0 1 :1405
- 2 - C 08 OR2 3 1 0 1 :1419
- 3 - C 07 OR2 1 3 1 1 :1429
- 3 - A 20 AND2 s 1 1 0 3 ~1732~1
- 2 - A 17 AND2 s 1 1 0 4 ~1732~2
- 2 - A 13 AND2 s 1 1 0 2 ~1732~3
- 4 - A 14 AND2 1 3 0 5 :1732
- 7 - A 14 OR2 0 3 0 2 :2464
- 5 - A 20 AND2 s 2 0 0 3 ~2466~1
- 6 - A 14 AND2 s 0 2 0 1 ~2466~2
- 2 - A 14 OR2 0 3 0 1 :2485
- 3 - A 14 OR2 0 3 0 3 :2500
- 1 - A 17 AND2 s 2 0 0 6 ~2502~1
- 4 - A 13 OR2 2 2 0 1 :2515
- 7 - A 19 AND2 s 2 0 0 1 ~2526~1
- 5 - A 13 OR2 2 2 0 1 :2527
- 3 - A 13 OR2 0 3 0 3 :2536
- 2 - A 19 OR2 3 1 0 1 :2548
- 4 - A 19 OR2 3 1 0 1 :2562
- 5 - A 19 OR2 3 1 0 1 :2566
- 1 - A 19 OR2 0 3 0 3 :2572
- 1 - A 16 AND2 s 1 1 0 6 ~2574~1
- 7 - A 17 OR2 3 1 0 1 :2589
- 8 - A 17 OR2 0 4 1 1 :2608
- 1 - A 13 AND2 s 1 1 0 4 ~2610~1
- 6 - A 17 OR2 3 1 0 1 :2625
- 4 - A 17 OR2 0 4 1 1 :2644
- 6 - A 19 OR2 3 1 0 1 :2661
- 8 - A 19 OR2 2 2 0 1 :2673
- 3 - A 19 OR2 2 2 1 1 :2680
- 7 - A 20 OR2 2 1 0 1 :2689
- 8 - A 20 OR2 2 2 0 1 :2706
- 4 - A 20 OR2 1 3 1 1 :2716
- 3 - A 17 OR2 s 3 1 0 1 ~2740~1
- 5 - A 17 OR2 1 2 1 0 :2752
- 6 - A 20 OR2 3 1 0 1 :2764
- 1 - A 21 AND2 s ! 0 2 0 3 ~2788~1
- 1 - A 20 OR2 1 3 1 1 :2788
- 2 - A 20 AND2 s ! 2 0 0 4 ~2800~1
- 6 - A 13 OR2 3 1 0 1 :2800
- 7 - A 13 OR2 3 1 0 1 :2814
- 8 - A 13 OR2 1 3 1 1 :2824
- 3 - B 03 OR2 ! 1 2 0 8 :2889
- 5 - C 01 OR2 0 2 0 1 :2985
- 4 - C 01 OR2 0 2 0 1 :2991
- 7 - C 01 OR2 0 2 0 1 :2997
- 6 - C 01 OR2 0 2 0 1 :3003
- 8 - A 14 OR2 0 2 0 1 :3009
- 5 - A 14 OR2 0 2 0 1 :3015
- 3 - A 15 OR2 0 2 0 1 :3021
- 1 - A 15 OR2 0 2 0 1 :3027
- 2 - C 01 OR2 s 0 4 0 1 ~3119~1
- 3 - C 01 OR2 s 0 4 0 1 ~3119~2
- 1 - A 14 OR2 s 0 4 0 1 ~3119~3
- 2 - A 15 OR2 s 0 4 0 1 ~3119~4
- 4 - B 03 AND2 s 1 2 0 2 ~3119~5
- 1 - C 01 AND2 0 4 0 2 :3119
- 8 - B 03 OR2 1 2 0 1 :3176
- 2 - B 03 AND2 s 1 2 0 1 ~3193~1
- 7 - B 03 OR2 2 0 0 3 :3219
- 1 - B 03 OR2 2 2 1 1 :3225
- 5 - B 03 OR2 2 1 0 2 :3231
- 4 - B 12 OR2 2 1 1 0 :3237
- 6 - B 03 OR2 2 1 0 1 :3255
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\maxplus\shuzi\lock.rpt
lock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/ 96( 8%) 0/ 48( 0%) 14/ 48( 29%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
B: 2/ 96( 2%) 4/ 48( 8%) 0/ 48( 0%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
C: 13/ 96( 13%) 21/ 48( 43%) 0/ 48( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus\shuzi\lock.rpt
lock
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
a4 : INPUT;
a5 : INPUT;
a6 : INPUT;
a7 : INPUT;
a8 : INPUT;
a9 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
b4 : INPUT;
b5 : INPUT;
b6 : INPUT;
b7 : INPUT;
b8 : INPUT;
b9 : INPUT;
en : INPUT;
enl : INPUT;
-- Node name is 'c0'
-- Equation name is 'c0', type is output
c0 = _LC3_C7;
-- Node name is 'c1'
-- Equation name is 'c1', type is output
c1 = _LC1_C9;
-- Node name is 'c2'
-- Equation name is 'c2', type is output
c2 = _LC8_C7;
-- Node name is 'c3'
-- Equation name is 'c3', type is output
c3 = _LC6_C3;
-- Node name is 'c4'
-- Equation name is 'c4', type is output
c4 = _LC7_C7;
-- Node name is 'c5'
-- Equation name is 'c5', type is output
c5 = _LC8_C6;
-- Node name is 'c6'
-- Equation name is 'c6', type is output
c6 = _LC2_C3;
-- Node name is 'd0'
-- Equation name is 'd0', type is output
d0 = _LC8_A13;
-- Node name is 'd1'
-- Equation name is 'd1', type is output
d1 = _LC1_A20;
-- Node name is 'd2'
-- Equation name is 'd2', type is output
d2 = _LC5_A17;
-- Node name is 'd3'
-- Equation name is 'd3', type is output
d3 = _LC4_A20;
-- Node name is 'd4'
-- Equation name is 'd4', type is output
d4 = _LC3_A19;
-- Node name is 'd5'
-- Equation name is 'd5', type is output
d5 = _LC4_A17;
-- Node name is 'd6'
-- Equation name is 'd6', type is output
d6 = _LC8_A17;
-- Node name is 'k'
-- Equation name is 'k', type is output
k = _LC1_B3;
-- Node name is 'm'
-- Equation name is 'm', type is output
m = _LC4_B12;
-- Node name is '~337~1'
-- Equation name is '~337~1', location is LC4_C9, type is buried.
-- synthesized logic cell
_LC4_C9 = LCELL( _EQ001);
_EQ001 = !a4 & _LC4_C8;
-- Node name is '~337~2'
-- Equation name is '~337~2', location is LC4_C6, type is buried.
-- synthesized logic cell
_LC4_C6 = LCELL( _EQ002);
_EQ002 = !a1 & _LC5_C7;
-- Node name is ':337'
-- Equation name is '_LC2_C6', type is buried
_LC2_C6 = LCELL( _EQ003);
_EQ003 = !a0 & !a1 & !_LC3_C6 & _LC5_C7;
-- Node name is ':1069'
-- Equation name is '_LC3_C9', type is buried
_LC3_C9 = LCELL( _EQ004);
_EQ004 = _LC2_C6 & _LC3_C9
# _LC3_C9 & _LC7_C9
# _LC1_C3 & _LC7_C9;
-- Node name is '~1071~1'
-- Equation name is '~1071~1', location is LC4_C8, type is buried.
-- synthesized logic cell
_LC4_C8 = LCELL( _EQ005);
_EQ005 = !a5 & !a6;
-- Node name is '~1071~2'
-- Equation name is '~1071~2', location is LC7_C9, type is buried.
-- synthesized logic cell
_LC7_C9 = LCELL( _EQ006);
_EQ006 = !a7 & _LC4_C9 & !_LC6_C9;
-- Node name is ':1090'
-- Equation name is '_LC5_C9', type is buried
_LC5_C9 = LCELL( _EQ007);
_EQ007 = a7
# !_LC4_C9
# !_LC1_C3 & _LC2_C9;
-- Node name is ':1105'
-- Equation name is '_LC2_C9', type is buried
_LC2_C9 = LCELL( _EQ008);
_EQ008 = _LC5_C9 & !_LC6_C9
# _LC2_C6 & _LC2_C9;
-- Node name is '~1107~1'
-- Equation name is '~1107~1', location is LC5_C7, type is buried.
-- synthesized logic cell
_LC5_C7 = LCELL( _EQ009);
_EQ009 = !a2 & !a3;
-- Node name is ':1120'
-- Equation name is '_LC6_C8', type is buried
_LC6_C8 = LCELL( _EQ010);
_EQ010 = !_LC1_C3 & _LC5_C8
# a6
# a7;
-- Node name is '~1131~1'
-- Equation name is '~1131~1', location is LC1_C8, type is buried.
-- synthesized logic cell
_LC1_C8 = LCELL( _EQ011);
_EQ011 = !a4 & !a5;
-- Node name is ':1132'
-- Equation name is '_LC7_C8', type is buried
_LC7_C8 = LCELL( _EQ012);
_EQ012 = !a4 & !a5 & _LC6_C8
# !_LC5_C7;
-- Node name is ':1141'
-- Equation name is '_LC5_C8', type is buried
_LC5_C8 = LCELL( _EQ013);
_EQ013 = _LC2_C7 & _LC7_C8
# _LC2_C6 & _LC5_C8;
-- Node name is ':1153'
-- Equation name is '_LC1_C11', type is buried
_LC1_C11 = LCELL( _EQ014);
_EQ014 = a7
# !a8 & a9
# !a8 & _LC2_C11;
-- Node name is ':1167'
-- Equation name is '_LC3_C8', type is buried
_LC3_C8 = LCELL( _EQ015);
_EQ015 = !a4 & a5
# !a4 & !a6 & _LC1_C11;
-- Node name is ':1171'
-- Equation name is '_LC1_C7', type is buried
_LC1_C7 = LCELL( _EQ016);
_EQ016 = a1
# !a2 & a3
# !a2 & _LC3_C8;
-- Node name is ':1177'
-- Equation name is '_LC2_C11', type is buried
_LC2_C11 = LCELL( _EQ017);
_EQ017 = _LC1_C6 & _LC1_C7
# _LC2_C6 & _LC2_C11;
-- Node name is '~1179~1'
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